Simulation Results: aes/masked

 
02/04/2026 16:07:25 DVSim: v1.17.3 sha: 08f559e json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 86.94 %
  • code
  • 95.24 %
  • assert
  • 98.29 %
  • func
  • 67.28 %
  • block
  • 95.91 %
  • line
  • 97.61 %
  • branch
  • 89.82 %
  • toggle
  • 98.05 %
  • FSM
  • 95.48 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
V3
0.00%
Testpoint Test Max Runtime Sim Time Pass Total %
wake_up 1 1 100.00
aes_wake_up 3.000s 87.541us 1 1 100.00
smoke 1 1 100.00
aes_smoke 2.000s 80.942us 1 1 100.00
csr_hw_reset 1 1 100.00
aes_csr_hw_reset 1.000s 80.878us 1 1 100.00
csr_rw 1 1 100.00
aes_csr_rw 2.000s 93.971us 1 1 100.00
csr_bit_bash 1 1 100.00
aes_csr_bit_bash 4.000s 383.273us 1 1 100.00
csr_aliasing 1 1 100.00
aes_csr_aliasing 2.000s 152.645us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
aes_csr_mem_rw_with_rand_reset 2.000s 103.151us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
aes_csr_rw 2.000s 93.971us 1 1 100.00
aes_csr_aliasing 2.000s 152.645us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
algorithm 3 3 100.00
aes_smoke 2.000s 80.942us 1 1 100.00
aes_config_error 3.000s 154.592us 1 1 100.00
aes_stress 3.000s 82.479us 1 1 100.00
key_length 3 3 100.00
aes_smoke 2.000s 80.942us 1 1 100.00
aes_config_error 3.000s 154.592us 1 1 100.00
aes_stress 3.000s 82.479us 1 1 100.00
back2back 2 2 100.00
aes_stress 3.000s 82.479us 1 1 100.00
aes_b2b 8.000s 143.127us 1 1 100.00
backpressure 1 1 100.00
aes_stress 3.000s 82.479us 1 1 100.00
multi_message 4 4 100.00
aes_smoke 2.000s 80.942us 1 1 100.00
aes_config_error 3.000s 154.592us 1 1 100.00
aes_stress 3.000s 82.479us 1 1 100.00
aes_alert_reset 6.000s 879.308us 1 1 100.00
failure_test 3 3 100.00
aes_man_cfg_err 3.000s 232.957us 1 1 100.00
aes_config_error 3.000s 154.592us 1 1 100.00
aes_alert_reset 6.000s 879.308us 1 1 100.00
trigger_clear_test 1 1 100.00
aes_clear 7.000s 406.695us 1 1 100.00
nist_test_vectors 1 1 100.00
aes_nist_vectors 7.000s 976.186us 1 1 100.00
nist_test_vectors_gcm 1 1 100.00
aes_nist_vectors_gcm 8.000s 1867.810us 1 1 100.00
reset_recovery 1 1 100.00
aes_alert_reset 6.000s 879.308us 1 1 100.00
stress 1 1 100.00
aes_stress 3.000s 82.479us 1 1 100.00
sideload 2 2 100.00
aes_stress 3.000s 82.479us 1 1 100.00
aes_sideload 4.000s 264.797us 1 1 100.00
deinitialization 1 1 100.00
aes_deinit 3.000s 226.480us 1 1 100.00
stress_all 1 1 100.00
aes_stress_all 3.000s 186.707us 1 1 100.00
gcm_save_and_restore 1 1 100.00
aes_gcm_save_restore 3.000s 206.301us 1 1 100.00
alert_test 1 1 100.00
aes_alert_test 2.000s 112.093us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
aes_tl_errors 2.000s 70.000us 1 1 100.00
tl_d_illegal_access 1 1 100.00
aes_tl_errors 2.000s 70.000us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
aes_csr_hw_reset 1.000s 80.878us 1 1 100.00
aes_csr_rw 2.000s 93.971us 1 1 100.00
aes_csr_aliasing 2.000s 152.645us 1 1 100.00
aes_same_csr_outstanding 3.000s 205.855us 1 1 100.00
tl_d_partial_access 4 4 100.00
aes_csr_hw_reset 1.000s 80.878us 1 1 100.00
aes_csr_rw 2.000s 93.971us 1 1 100.00
aes_csr_aliasing 2.000s 152.645us 1 1 100.00
aes_same_csr_outstanding 3.000s 205.855us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
reseeding 1 1 100.00
aes_reseed 5.000s 255.312us 1 1 100.00
fault_inject 3 3 100.00
aes_fi 4.000s 507.332us 1 1 100.00
aes_control_fi 2.000s 55.431us 1 1 100.00
aes_cipher_fi 2.000s 51.569us 1 1 100.00
shadow_reg_update_error 1 1 100.00
aes_shadow_reg_errors 2.000s 102.893us 1 1 100.00
shadow_reg_read_clear_staged_value 1 1 100.00
aes_shadow_reg_errors 2.000s 102.893us 1 1 100.00
shadow_reg_storage_error 1 1 100.00
aes_shadow_reg_errors 2.000s 102.893us 1 1 100.00
shadowed_reset_glitch 1 1 100.00
aes_shadow_reg_errors 2.000s 102.893us 1 1 100.00
shadow_reg_update_error_with_csr_rw 1 1 100.00
aes_shadow_reg_errors_with_csr_rw 3.000s 200.716us 1 1 100.00
tl_intg_err 2 2 100.00
aes_tl_intg_err 2.000s 183.249us 1 1 100.00
aes_sec_cm 7.000s 729.640us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
aes_tl_intg_err 2.000s 183.249us 1 1 100.00
sec_cm_lc_escalate_en_intersig_mubi 1 1 100.00
aes_alert_reset 6.000s 879.308us 1 1 100.00
sec_cm_main_config_shadow 1 1 100.00
aes_shadow_reg_errors 2.000s 102.893us 1 1 100.00
sec_cm_gcm_config_shadow 1 1 100.00
aes_shadow_reg_errors 2.000s 102.893us 1 1 100.00
sec_cm_main_config_sparse 4 4 100.00
aes_smoke 2.000s 80.942us 1 1 100.00
aes_stress 3.000s 82.479us 1 1 100.00
aes_alert_reset 6.000s 879.308us 1 1 100.00
aes_core_fi 3.000s 269.967us 1 1 100.00
sec_cm_gcm_config_sparse 4 4 100.00
aes_gcm_save_restore 3.000s 206.301us 1 1 100.00
aes_config_error 3.000s 154.592us 1 1 100.00
aes_stress 3.000s 82.479us 1 1 100.00
aes_core_fi 3.000s 269.967us 1 1 100.00
sec_cm_aux_config_shadow 1 1 100.00
aes_shadow_reg_errors 2.000s 102.893us 1 1 100.00
sec_cm_aux_config_regwen 2 2 100.00
aes_readability 3.000s 69.685us 1 1 100.00
aes_stress 3.000s 82.479us 1 1 100.00
sec_cm_key_sideload 2 2 100.00
aes_stress 3.000s 82.479us 1 1 100.00
aes_sideload 4.000s 264.797us 1 1 100.00
sec_cm_key_sw_unreadable 1 1 100.00
aes_readability 3.000s 69.685us 1 1 100.00
sec_cm_data_reg_sw_unreadable 1 1 100.00
aes_readability 3.000s 69.685us 1 1 100.00
sec_cm_key_sec_wipe 1 1 100.00
aes_readability 3.000s 69.685us 1 1 100.00
sec_cm_iv_config_sec_wipe 1 1 100.00
aes_readability 3.000s 69.685us 1 1 100.00
sec_cm_data_reg_sec_wipe 1 1 100.00
aes_readability 3.000s 69.685us 1 1 100.00
sec_cm_data_reg_key_sca 1 1 100.00
aes_stress 3.000s 82.479us 1 1 100.00
sec_cm_key_masking 1 1 100.00
aes_stress 3.000s 82.479us 1 1 100.00
sec_cm_main_fsm_sparse 1 1 100.00
aes_fi 4.000s 507.332us 1 1 100.00
sec_cm_main_fsm_redun 4 4 100.00
aes_fi 4.000s 507.332us 1 1 100.00
aes_control_fi 2.000s 55.431us 1 1 100.00
aes_cipher_fi 2.000s 51.569us 1 1 100.00
aes_ctr_fi 2.000s 78.605us 1 1 100.00
sec_cm_cipher_fsm_sparse 1 1 100.00
aes_fi 4.000s 507.332us 1 1 100.00
sec_cm_cipher_fsm_redun 3 3 100.00
aes_fi 4.000s 507.332us 1 1 100.00
aes_control_fi 2.000s 55.431us 1 1 100.00
aes_cipher_fi 2.000s 51.569us 1 1 100.00
sec_cm_cipher_ctr_redun 1 1 100.00
aes_cipher_fi 2.000s 51.569us 1 1 100.00
sec_cm_ctr_fsm_sparse 1 1 100.00
aes_fi 4.000s 507.332us 1 1 100.00
sec_cm_ctr_fsm_redun 3 3 100.00
aes_fi 4.000s 507.332us 1 1 100.00
aes_control_fi 2.000s 55.431us 1 1 100.00
aes_ctr_fi 2.000s 78.605us 1 1 100.00
sec_cm_ghash_fsm_sparse 1 1 100.00
aes_fi 4.000s 507.332us 1 1 100.00
sec_cm_ctrl_sparse 4 4 100.00
aes_fi 4.000s 507.332us 1 1 100.00
aes_control_fi 2.000s 55.431us 1 1 100.00
aes_cipher_fi 2.000s 51.569us 1 1 100.00
aes_ctr_fi 2.000s 78.605us 1 1 100.00
sec_cm_main_fsm_global_esc 1 1 100.00
aes_alert_reset 6.000s 879.308us 1 1 100.00
sec_cm_main_fsm_local_esc 4 4 100.00
aes_fi 4.000s 507.332us 1 1 100.00
aes_control_fi 2.000s 55.431us 1 1 100.00
aes_cipher_fi 2.000s 51.569us 1 1 100.00
aes_ctr_fi 2.000s 78.605us 1 1 100.00
sec_cm_cipher_fsm_local_esc 4 4 100.00
aes_fi 4.000s 507.332us 1 1 100.00
aes_control_fi 2.000s 55.431us 1 1 100.00
aes_cipher_fi 2.000s 51.569us 1 1 100.00
aes_ctr_fi 2.000s 78.605us 1 1 100.00
sec_cm_ctr_fsm_local_esc 3 3 100.00
aes_fi 4.000s 507.332us 1 1 100.00
aes_control_fi 2.000s 55.431us 1 1 100.00
aes_ctr_fi 2.000s 78.605us 1 1 100.00
sec_cm_ghash_fsm_local_esc 2 2 100.00
aes_fi 4.000s 507.332us 1 1 100.00
aes_ghash_fi 2.000s 71.722us 1 1 100.00
sec_cm_data_reg_local_esc 3 3 100.00
aes_fi 4.000s 507.332us 1 1 100.00
aes_control_fi 2.000s 55.431us 1 1 100.00
aes_cipher_fi 2.000s 51.569us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 0 1 0.00
aes_stress_all_with_rand_reset 11.000s 595.652us 0 1 0.00

Error Messages

   Test seed line log context
UVM_ERROR (cip_base_vseq.sv:1237) [aes_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses.
aes_stress_all_with_rand_reset 4124478744359732661923755449598899732512511275086893602950085513862688577656 236
UVM_ERROR @ 595651634 ps: (cip_base_vseq.sv:1237) [uvm_test_top.env.virtual_sequencer.aes_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 595651634 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---