Simulation Results: alert_handler

 
02/04/2026 16:07:25 DVSim: v1.17.3 sha: 08f559e json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 79.50 %
  • code
  • 88.02 %
  • assert
  • 97.29 %
  • func
  • 53.20 %
  • block
  • 98.19 %
  • line
  • 99.54 %
  • branch
  • 96.49 %
  • toggle
  • 80.26 %
  • FSM
  • 75.79 %
Validation stages
V1
100.00%
V2
89.47%
V2S
100.00%
V3
0.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
alert_handler_smoke 39.000s 264.856us 1 1 100.00
csr_hw_reset 1 1 100.00
alert_handler_csr_hw_reset 13.000s 116.730us 1 1 100.00
csr_rw 1 1 100.00
alert_handler_csr_rw 6.000s 24.692us 1 1 100.00
csr_bit_bash 1 1 100.00
alert_handler_csr_bit_bash 646.000s 9881.549us 1 1 100.00
csr_aliasing 1 1 100.00
alert_handler_csr_aliasing 165.000s 5055.780us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
alert_handler_csr_mem_rw_with_rand_reset 15.000s 483.249us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
alert_handler_csr_rw 6.000s 24.692us 1 1 100.00
alert_handler_csr_aliasing 165.000s 5055.780us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
esc_accum 1 1 100.00
alert_handler_esc_alert_accum 29.000s 202.999us 1 1 100.00
esc_timeout 1 1 100.00
alert_handler_esc_intr_timeout 102.000s 1402.927us 1 1 100.00
entropy 1 1 100.00
alert_handler_entropy 3263.000s 33781.432us 1 1 100.00
sig_int_fail 1 1 100.00
alert_handler_sig_int_fail 7.000s 133.696us 1 1 100.00
clk_skew 1 1 100.00
alert_handler_smoke 39.000s 264.856us 1 1 100.00
random_alerts 1 1 100.00
alert_handler_random_alerts 62.000s 758.747us 1 1 100.00
random_classes 1 1 100.00
alert_handler_random_classes 73.000s 2161.490us 1 1 100.00
ping_timeout 0 1 0.00
alert_handler_ping_timeout 21.000s 330.346us 0 1 0.00
lpg 2 2 100.00
alert_handler_lpg 1628.000s 13331.251us 1 1 100.00
alert_handler_lpg_stub_clk 2425.000s 13342.195us 1 1 100.00
stress_all 1 1 100.00
alert_handler_stress_all 39.000s 2168.966us 1 1 100.00
alert_handler_entropy_stress_test 1 1 100.00
alert_handler_entropy_stress 20.000s 327.345us 1 1 100.00
alert_handler_alert_accum_saturation 0 1 0.00
alert_handler_alert_accum_saturation 2.000s 0.000us 0 1 0.00
intr_test 1 1 100.00
alert_handler_intr_test 3.000s 34.886us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
alert_handler_tl_errors 16.000s 195.400us 1 1 100.00
tl_d_illegal_access 1 1 100.00
alert_handler_tl_errors 16.000s 195.400us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
alert_handler_csr_hw_reset 13.000s 116.730us 1 1 100.00
alert_handler_csr_rw 6.000s 24.692us 1 1 100.00
alert_handler_csr_aliasing 165.000s 5055.780us 1 1 100.00
alert_handler_same_csr_outstanding 56.000s 2305.630us 1 1 100.00
tl_d_partial_access 4 4 100.00
alert_handler_csr_hw_reset 13.000s 116.730us 1 1 100.00
alert_handler_csr_rw 6.000s 24.692us 1 1 100.00
alert_handler_csr_aliasing 165.000s 5055.780us 1 1 100.00
alert_handler_same_csr_outstanding 56.000s 2305.630us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
shadow_reg_update_error 1 1 100.00
alert_handler_shadow_reg_errors 159.000s 2476.200us 1 1 100.00
shadow_reg_read_clear_staged_value 1 1 100.00
alert_handler_shadow_reg_errors 159.000s 2476.200us 1 1 100.00
shadow_reg_storage_error 1 1 100.00
alert_handler_shadow_reg_errors 159.000s 2476.200us 1 1 100.00
shadowed_reset_glitch 1 1 100.00
alert_handler_shadow_reg_errors 159.000s 2476.200us 1 1 100.00
shadow_reg_update_error_with_csr_rw 1 1 100.00
alert_handler_shadow_reg_errors_with_csr_rw 770.000s 35325.401us 1 1 100.00
tl_intg_err 2 2 100.00
alert_handler_sec_cm 13.000s 1047.255us 1 1 100.00
alert_handler_tl_intg_err 6.000s 45.817us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
alert_handler_tl_intg_err 6.000s 45.817us 1 1 100.00
sec_cm_config_shadow 1 1 100.00
alert_handler_shadow_reg_errors 159.000s 2476.200us 1 1 100.00
sec_cm_ping_timer_config_regwen 1 1 100.00
alert_handler_smoke 39.000s 264.856us 1 1 100.00
sec_cm_alert_config_regwen 1 1 100.00
alert_handler_smoke 39.000s 264.856us 1 1 100.00
sec_cm_alert_loc_config_regwen 1 1 100.00
alert_handler_smoke 39.000s 264.856us 1 1 100.00
sec_cm_class_config_regwen 1 1 100.00
alert_handler_smoke 39.000s 264.856us 1 1 100.00
sec_cm_alert_intersig_diff 1 1 100.00
alert_handler_sig_int_fail 7.000s 133.696us 1 1 100.00
sec_cm_lpg_intersig_mubi 1 1 100.00
alert_handler_lpg 1628.000s 13331.251us 1 1 100.00
sec_cm_esc_intersig_diff 1 1 100.00
alert_handler_sig_int_fail 7.000s 133.696us 1 1 100.00
sec_cm_alert_rx_intersig_bkgn_chk 1 1 100.00
alert_handler_entropy 3263.000s 33781.432us 1 1 100.00
sec_cm_esc_tx_intersig_bkgn_chk 1 1 100.00
alert_handler_entropy 3263.000s 33781.432us 1 1 100.00
sec_cm_esc_timer_fsm_sparse 1 1 100.00
alert_handler_sec_cm 13.000s 1047.255us 1 1 100.00
sec_cm_ping_timer_fsm_sparse 1 1 100.00
alert_handler_sec_cm 13.000s 1047.255us 1 1 100.00
sec_cm_esc_timer_fsm_local_esc 1 1 100.00
alert_handler_sec_cm 13.000s 1047.255us 1 1 100.00
sec_cm_ping_timer_fsm_local_esc 1 1 100.00
alert_handler_sec_cm 13.000s 1047.255us 1 1 100.00
sec_cm_esc_timer_fsm_global_esc 1 1 100.00
alert_handler_sec_cm 13.000s 1047.255us 1 1 100.00
sec_cm_accu_ctr_redun 1 1 100.00
alert_handler_sec_cm 13.000s 1047.255us 1 1 100.00
sec_cm_esc_timer_ctr_redun 1 1 100.00
alert_handler_sec_cm 13.000s 1047.255us 1 1 100.00
sec_cm_ping_timer_ctr_redun 1 1 100.00
alert_handler_sec_cm 13.000s 1047.255us 1 1 100.00
sec_cm_ping_timer_lfsr_redun 1 1 100.00
alert_handler_sec_cm 13.000s 1047.255us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 0 1 0.00
alert_handler_stress_all_with_rand_reset 126.000s 7177.090us 0 1 0.00

Error Messages

   Test seed line log context
UVM_ERROR (alert_handler_scoreboard.sv:595) [scoreboard] Check failed crashdump_val.loc_alert_cause[i] == ral.loc_alert_cause[i].get_mirrored_value() (* [*] vs * [*])
alert_handler_ping_timeout 10451143417510689696405356990768261715993435174945357325134423247781635851579 89
UVM_ERROR @ 330346139 ps: (alert_handler_scoreboard.sv:595) [uvm_test_top.env.scoreboard] Check failed crashdump_val.loc_alert_cause[i] == ral.loc_alert_cause[i].get_mirrored_value() (1 [0x1] vs 0 [0x0])
UVM_INFO @ 330346139 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (uvm_hdl_inca.c:743) [UVM/DPI/NOBJ3] name tb.dut.gen_classes[``i``].u_accu.u_prim_count.cnt_q[*] cannot be resolved to a hdl object (vlog,vhdl,vlog-slice)
alert_handler_alert_accum_saturation 38556489144788900141763930187830734502480260608809825652319807919481301253740 88
UVM_ERROR @ 0 ps: (uvm_hdl_inca.c:743) [UVM/DPI/NOBJ3] name tb.dut.gen_classes[``i``].u_accu.u_prim_count.cnt_q[0] cannot be resolved to a hdl object (vlog,vhdl,vlog-slice)
UVM_INFO @ 0 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (alert_handler_scoreboard.sv:488) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) reg name: alert_handler_reg_block.classa_state
alert_handler_stress_all_with_rand_reset 54283228852869945429796835242916467867180424269348470235967498283821985390744 117
UVM_ERROR @ 7177089960 ps: (alert_handler_scoreboard.sv:488) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 4 [0x4]) reg name: alert_handler_reg_block.classa_state
UVM_INFO @ 7177089960 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---