| V1 |
|
0.00% |
| V2 |
|
0.00% |
| V2S |
|
0.00% |
| V3 |
|
0.00% |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| smoke | 0 | 1 | 0.00 | |||
| clkmgr_smoke | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| csr_hw_reset | 0 | 1 | 0.00 | |||
| clkmgr_csr_hw_reset | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| csr_rw | 0 | 1 | 0.00 | |||
| clkmgr_csr_rw | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| csr_bit_bash | 0 | 1 | 0.00 | |||
| clkmgr_csr_bit_bash | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| csr_aliasing | 0 | 1 | 0.00 | |||
| clkmgr_csr_aliasing | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| csr_mem_rw_with_rand_reset | 0 | 1 | 0.00 | |||
| clkmgr_csr_mem_rw_with_rand_reset | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| regwen_csr_and_corresponding_lockable_csr | 0 | 2 | 0.00 | |||
| clkmgr_csr_rw | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| clkmgr_csr_aliasing | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| peri_enables | 0 | 1 | 0.00 | |||
| clkmgr_peri | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| trans_enables | 0 | 1 | 0.00 | |||
| clkmgr_trans | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| clk_status | 0 | 1 | 0.00 | |||
| clkmgr_clk_status | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| jitter | 0 | 1 | 0.00 | |||
| clkmgr_smoke | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| frequency | 0 | 1 | 0.00 | |||
| clkmgr_frequency | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| frequency_timeout | 0 | 1 | 0.00 | |||
| clkmgr_frequency_timeout | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| frequency_overflow | 0 | 1 | 0.00 | |||
| clkmgr_frequency | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| stress_all | 0 | 1 | 0.00 | |||
| clkmgr_stress_all | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| alert_test | 0 | 1 | 0.00 | |||
| clkmgr_alert_test | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| tl_d_oob_addr_access | 0 | 1 | 0.00 | |||
| clkmgr_tl_errors | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| tl_d_illegal_access | 0 | 1 | 0.00 | |||
| clkmgr_tl_errors | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| tl_d_outstanding_access | 0 | 4 | 0.00 | |||
| clkmgr_csr_hw_reset | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| clkmgr_csr_rw | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| clkmgr_csr_aliasing | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| clkmgr_same_csr_outstanding | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| tl_d_partial_access | 0 | 4 | 0.00 | |||
| clkmgr_csr_hw_reset | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| clkmgr_csr_rw | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| clkmgr_csr_aliasing | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| clkmgr_same_csr_outstanding | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| tl_intg_err | 0 | 2 | 0.00 | |||
| clkmgr_sec_cm | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| clkmgr_tl_intg_err | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| shadow_reg_update_error | 0 | 1 | 0.00 | |||
| clkmgr_shadow_reg_errors | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| shadow_reg_read_clear_staged_value | 0 | 1 | 0.00 | |||
| clkmgr_shadow_reg_errors | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| shadow_reg_storage_error | 0 | 1 | 0.00 | |||
| clkmgr_shadow_reg_errors | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| shadowed_reset_glitch | 0 | 1 | 0.00 | |||
| clkmgr_shadow_reg_errors | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| shadow_reg_update_error_with_csr_rw | 0 | 1 | 0.00 | |||
| clkmgr_shadow_reg_errors_with_csr_rw | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| sec_cm_bus_integrity | 0 | 1 | 0.00 | |||
| clkmgr_tl_intg_err | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| sec_cm_meas_clk_bkgn_chk | 0 | 1 | 0.00 | |||
| clkmgr_frequency | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| sec_cm_timeout_clk_bkgn_chk | 0 | 1 | 0.00 | |||
| clkmgr_frequency_timeout | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| sec_cm_meas_config_shadow | 0 | 1 | 0.00 | |||
| clkmgr_shadow_reg_errors | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| sec_cm_idle_intersig_mubi | 0 | 1 | 0.00 | |||
| clkmgr_idle_intersig_mubi | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| sec_cm_jitter_config_mubi | 0 | 1 | 0.00 | |||
| clkmgr_csr_rw | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| sec_cm_idle_ctr_redun | 0 | 1 | 0.00 | |||
| clkmgr_sec_cm | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| sec_cm_meas_config_regwen | 0 | 1 | 0.00 | |||
| clkmgr_csr_rw | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| sec_cm_clk_ctrl_config_regwen | 0 | 1 | 0.00 | |||
| clkmgr_csr_rw | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| prim_count_check | 0 | 1 | 0.00 | |||
| clkmgr_sec_cm | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| regwen | 0 | 1 | 0.00 | |||
| clkmgr_regwen | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| stress_all_with_rand_reset | 0 | 1 | 0.00 | |||
| clkmgr_stress_all_with_rand_reset | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| Test | seed | line | log context | |
|---|---|---|---|---|
| xmvlog: *E,ENUMERR (src/lowrisc_darjeeling_dv_clkmgr_env_*/seq_lib/clkmgr_regwen_vseq.sv,*|52): This assignment is a violation of SystemVerilog strong typing rules for enumeration datatypes. | ||||
| default | None | 1005 |
xmvlog: *E,ENUMERR (src/lowrisc_darjeeling_dv_clkmgr_env_0.1/seq_lib/clkmgr_regwen_vseq.sv,21|52): This assignment is a violation of SystemVerilog strong typing rules for enumeration datatypes.
package worklib.clkmgr_env_pkg:sv
errors: 1, warnings: 2
file: src/lowrisc_darjeeling_dv_clkmgr_env_0.1/clkmgr_if.sv
import clkmgr_env_pkg::*;
|
|
| cover_reg_top | None | 1005 |
xmvlog: *E,ENUMERR (src/lowrisc_darjeeling_dv_clkmgr_env_0.1/seq_lib/clkmgr_regwen_vseq.sv,21|52): This assignment is a violation of SystemVerilog strong typing rules for enumeration datatypes.
package worklib.clkmgr_env_pkg:sv
errors: 1, warnings: 2
file: src/lowrisc_darjeeling_dv_clkmgr_env_0.1/clkmgr_if.sv
import clkmgr_env_pkg::*;
|
|
| Job killed most likely because its dependent job failed. | ||||
| clkmgr_smoke | 81475118043611484670652234257154843652649041507760333683908783051387607525264 | None | ||
| clkmgr_frequency | 3938590731610606718297220290834761862110556321072991727528521491013228880736 | None | ||
| clkmgr_frequency_timeout | 9457177155994357502528329656676075807794392775323834501153074743956048680525 | None | ||
| clkmgr_peri | 30934678652810918060685476860110778919020611394453717651088401468808888435286 | None | ||
| clkmgr_trans | 85314298709913834742794387172291702287608786038195010321999848787893256039391 | None | ||
| clkmgr_clk_status | 84919204355916520135509886111239198211237483146674290575578508949815464168976 | None | ||
| clkmgr_idle_intersig_mubi | 76212792004369167215820400861593711792379174233429227170434343226088235826551 | None | ||
| clkmgr_regwen | 68458948563459157619954144583987994011039551191622133226455866947697038786793 | None | ||
| clkmgr_sec_cm | 37969573558889630708350106160791313276023392783936684208270438406300954212539 | None | ||
| clkmgr_stress_all_with_rand_reset | 81617451097278227397170017451760677869890957459345276621645847257189657607372 | None | ||
| clkmgr_stress_all | 61121356700624912644294201199019262311790756616205147204072469210597900700757 | None | ||
| clkmgr_alert_test | 69547650703154688810435064596331881761190801448245288434963918845682744580441 | None | ||
| clkmgr_shadow_reg_errors | 64376789575108698589228855040297308031415854432686640153797473349939841949626 | None | ||
| clkmgr_shadow_reg_errors_with_csr_rw | 22021299878204477560459008989757983972147247678461422378538368223313826375662 | None | ||
| clkmgr_tl_errors | 106039037980089979292945321411729779586092776468773538481391417227247863379540 | None | ||
| clkmgr_tl_intg_err | 25239722687544929016531367646426294875614380010313214641966277872706321455714 | None | ||
| clkmgr_csr_hw_reset | 57818554223250486718525064452048730514525930087695666531951080079953970988049 | None | ||
| clkmgr_csr_rw | 101421204827418895819105563867108717711688028515914485030762647256128925255319 | None | ||
| clkmgr_csr_bit_bash | 99861701332687318634985376097814335133932429166297470103103084764957477333154 | None | ||
| clkmgr_csr_aliasing | 34204723667605357850659663899190622933483644264357380817062840071822510115978 | None | ||
| clkmgr_same_csr_outstanding | 85529955116122838408725603985837486527213415451426190099173164711700811740317 | None | ||
| clkmgr_csr_mem_rw_with_rand_reset | 50681366028238731942645977521254241364923114825577734485390645646096206086025 | None | ||
| clkmgr | None | None | ||
| clkmgr | None | None | ||