Simulation Results: csrng

 
02/04/2026 16:07:25 DVSim: v1.17.3 sha: 08f559e json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 87.87 %
  • code
  • 92.41 %
  • assert
  • 93.23 %
  • func
  • 77.96 %
  • block
  • 97.15 %
  • line
  • 97.80 %
  • branch
  • 92.84 %
  • toggle
  • 93.31 %
  • FSM
  • 85.71 %
Validation stages
V1
100.00%
V2
91.67%
V2S
100.00%
V3
0.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
csrng_smoke 2.000s 38.200us 1 1 100.00
csr_hw_reset 1 1 100.00
csrng_csr_hw_reset 2.000s 35.466us 1 1 100.00
csr_rw 1 1 100.00
csrng_csr_rw 3.000s 48.780us 1 1 100.00
csr_bit_bash 1 1 100.00
csrng_csr_bit_bash 22.000s 1127.609us 1 1 100.00
csr_aliasing 1 1 100.00
csrng_csr_aliasing 3.000s 52.006us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
csrng_csr_mem_rw_with_rand_reset 2.000s 23.637us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
csrng_csr_rw 3.000s 48.780us 1 1 100.00
csrng_csr_aliasing 3.000s 52.006us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
interrupts 1 1 100.00
csrng_intr 4.000s 75.312us 1 1 100.00
alerts 1 1 100.00
csrng_alert 8.000s 181.414us 1 1 100.00
err 1 1 100.00
csrng_err 3.000s 24.168us 1 1 100.00
cmds 0 1 0.00
csrng_cmds 3.000s 53.840us 0 1 0.00
life cycle 0 1 0.00
csrng_cmds 3.000s 53.840us 0 1 0.00
stress_all 1 1 100.00
csrng_stress_all 315.000s 18853.931us 1 1 100.00
intr_test 1 1 100.00
csrng_intr_test 2.000s 40.943us 1 1 100.00
alert_test 1 1 100.00
csrng_alert_test 2.000s 11.855us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
csrng_tl_errors 4.000s 54.445us 1 1 100.00
tl_d_illegal_access 1 1 100.00
csrng_tl_errors 4.000s 54.445us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
csrng_csr_hw_reset 2.000s 35.466us 1 1 100.00
csrng_csr_rw 3.000s 48.780us 1 1 100.00
csrng_csr_aliasing 3.000s 52.006us 1 1 100.00
csrng_same_csr_outstanding 2.000s 29.321us 1 1 100.00
tl_d_partial_access 4 4 100.00
csrng_csr_hw_reset 2.000s 35.466us 1 1 100.00
csrng_csr_rw 3.000s 48.780us 1 1 100.00
csrng_csr_aliasing 3.000s 52.006us 1 1 100.00
csrng_same_csr_outstanding 2.000s 29.321us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
csrng_tl_intg_err 5.000s 110.812us 1 1 100.00
csrng_sec_cm 3.000s 108.599us 1 1 100.00
sec_cm_config_regwen 2 2 100.00
csrng_csr_rw 3.000s 48.780us 1 1 100.00
csrng_regwen 2.000s 36.852us 1 1 100.00
sec_cm_config_mubi 1 1 100.00
csrng_alert 8.000s 181.414us 1 1 100.00
sec_cm_intersig_mubi 1 1 100.00
csrng_stress_all 315.000s 18853.931us 1 1 100.00
sec_cm_main_sm_fsm_sparse 3 3 100.00
csrng_intr 4.000s 75.312us 1 1 100.00
csrng_err 3.000s 24.168us 1 1 100.00
csrng_sec_cm 3.000s 108.599us 1 1 100.00
sec_cm_cmd_stage_fsm_sparse 3 3 100.00
csrng_intr 4.000s 75.312us 1 1 100.00
csrng_err 3.000s 24.168us 1 1 100.00
csrng_sec_cm 3.000s 108.599us 1 1 100.00
sec_cm_ctr_drbg_fsm_sparse 3 3 100.00
csrng_intr 4.000s 75.312us 1 1 100.00
csrng_err 3.000s 24.168us 1 1 100.00
csrng_sec_cm 3.000s 108.599us 1 1 100.00
sec_cm_ctr_drbg_ctr_redun 3 3 100.00
csrng_intr 4.000s 75.312us 1 1 100.00
csrng_err 3.000s 24.168us 1 1 100.00
csrng_sec_cm 3.000s 108.599us 1 1 100.00
sec_cm_gen_cmd_ctr_redun 3 3 100.00
csrng_intr 4.000s 75.312us 1 1 100.00
csrng_err 3.000s 24.168us 1 1 100.00
csrng_sec_cm 3.000s 108.599us 1 1 100.00
sec_cm_ctrl_mubi 1 1 100.00
csrng_alert 8.000s 181.414us 1 1 100.00
sec_cm_main_sm_ctr_local_esc 2 2 100.00
csrng_intr 4.000s 75.312us 1 1 100.00
csrng_err 3.000s 24.168us 1 1 100.00
sec_cm_constants_lc_gated 1 1 100.00
csrng_stress_all 315.000s 18853.931us 1 1 100.00
sec_cm_sw_genbits_bus_consistency 1 1 100.00
csrng_alert 8.000s 181.414us 1 1 100.00
sec_cm_tile_link_bus_integrity 1 1 100.00
csrng_tl_intg_err 5.000s 110.812us 1 1 100.00
sec_cm_aes_cipher_fsm_sparse 3 3 100.00
csrng_intr 4.000s 75.312us 1 1 100.00
csrng_err 3.000s 24.168us 1 1 100.00
csrng_sec_cm 3.000s 108.599us 1 1 100.00
sec_cm_aes_cipher_fsm_redun 2 2 100.00
csrng_intr 4.000s 75.312us 1 1 100.00
csrng_err 3.000s 24.168us 1 1 100.00
sec_cm_aes_cipher_ctrl_sparse 2 2 100.00
csrng_intr 4.000s 75.312us 1 1 100.00
csrng_err 3.000s 24.168us 1 1 100.00
sec_cm_aes_cipher_fsm_local_esc 2 2 100.00
csrng_intr 4.000s 75.312us 1 1 100.00
csrng_err 3.000s 24.168us 1 1 100.00
sec_cm_aes_cipher_ctr_redun 3 3 100.00
csrng_intr 4.000s 75.312us 1 1 100.00
csrng_err 3.000s 24.168us 1 1 100.00
csrng_sec_cm 3.000s 108.599us 1 1 100.00
sec_cm_aes_cipher_data_reg_local_esc 2 2 100.00
csrng_intr 4.000s 75.312us 1 1 100.00
csrng_err 3.000s 24.168us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 0 1 0.00
csrng_stress_all_with_rand_reset 0.000s 0.000us 0 1 0.00

Error Messages

   Test seed line log context
UVM_FATAL (csrng_scoreboard.sv:660) [scoreboard] Check failed cs_item[app].genbits_q[i] == prd_genbits_q[app][i] (* [*] vs * [*])
csrng_cmds 67053431019916832780733655116894059550276856769781846683791931475278959815733 130
UVM_FATAL @ 53840356 ps: (csrng_scoreboard.sv:660) [uvm_test_top.env.scoreboard] Check failed cs_item[app].genbits_q[i] == prd_genbits_q[app][i] (0 [0x0] vs 45084041148535030531952847123503232606 [0x21eaded82eeb1ca61225dcab33d5b65e])
UVM_INFO @ 53840356 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Job timed out after * minutes
csrng_stress_all_with_rand_reset 36972167748845955485278380985804704096327874774527881794524710869656708950829 None
Job timed out after 180 minutes