Simulation Results: edn/edn0

 
02/04/2026 16:07:25 DVSim: v1.17.3 sha: 08f559e json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 79.28 %
  • code
  • 92.08 %
  • assert
  • 96.24 %
  • func
  • 49.51 %
  • block
  • 95.99 %
  • line
  • 98.10 %
  • branch
  • 91.20 %
  • toggle
  • 84.45 %
  • FSM
  • 94.57 %
Validation stages
V1
100.00%
V2
92.86%
V2S
100.00%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
edn_smoke 1.000s 18.397us 1 1 100.00
csr_hw_reset 1 1 100.00
edn_csr_hw_reset 7.000s 22.400us 1 1 100.00
csr_rw 1 1 100.00
edn_csr_rw 1.000s 13.657us 1 1 100.00
csr_bit_bash 1 1 100.00
edn_csr_bit_bash 5.000s 258.197us 1 1 100.00
csr_aliasing 1 1 100.00
edn_csr_aliasing 2.000s 52.966us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
edn_csr_mem_rw_with_rand_reset 2.000s 46.537us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
edn_csr_rw 1.000s 13.657us 1 1 100.00
edn_csr_aliasing 2.000s 52.966us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
firmware 1 1 100.00
edn_genbits 1.000s 32.538us 1 1 100.00
csrng_commands 1 1 100.00
edn_genbits 1.000s 32.538us 1 1 100.00
genbits 1 1 100.00
edn_genbits 1.000s 32.538us 1 1 100.00
interrupts 1 1 100.00
edn_intr 2.000s 20.484us 1 1 100.00
alerts 1 1 100.00
edn_alert 1.000s 29.035us 1 1 100.00
errs 0 1 0.00
edn_err 1.000s 1.905us 0 1 0.00
disable 2 2 100.00
edn_disable 1.000s 106.214us 1 1 100.00
edn_disable_auto_req_mode 1.000s 236.524us 1 1 100.00
stress_all 1 1 100.00
edn_stress_all 3.000s 115.536us 1 1 100.00
intr_test 1 1 100.00
edn_intr_test 8.000s 56.859us 1 1 100.00
alert_test 1 1 100.00
edn_alert_test 2.000s 11.941us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
edn_tl_errors 8.000s 69.972us 1 1 100.00
tl_d_illegal_access 1 1 100.00
edn_tl_errors 8.000s 69.972us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
edn_csr_hw_reset 7.000s 22.400us 1 1 100.00
edn_csr_rw 1.000s 13.657us 1 1 100.00
edn_csr_aliasing 2.000s 52.966us 1 1 100.00
edn_same_csr_outstanding 2.000s 17.325us 1 1 100.00
tl_d_partial_access 4 4 100.00
edn_csr_hw_reset 7.000s 22.400us 1 1 100.00
edn_csr_rw 1.000s 13.657us 1 1 100.00
edn_csr_aliasing 2.000s 52.966us 1 1 100.00
edn_same_csr_outstanding 2.000s 17.325us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
edn_tl_intg_err 9.000s 106.882us 1 1 100.00
edn_sec_cm 7.000s 2335.142us 1 1 100.00
sec_cm_config_regwen 1 1 100.00
edn_regwen 2.000s 19.462us 1 1 100.00
sec_cm_config_mubi 1 1 100.00
edn_alert 1.000s 29.035us 1 1 100.00
sec_cm_main_sm_fsm_sparse 1 1 100.00
edn_sec_cm 7.000s 2335.142us 1 1 100.00
sec_cm_ack_sm_fsm_sparse 1 1 100.00
edn_sec_cm 7.000s 2335.142us 1 1 100.00
sec_cm_fifo_ctr_redun 1 1 100.00
edn_sec_cm 7.000s 2335.142us 1 1 100.00
sec_cm_ctr_redun 1 1 100.00
edn_sec_cm 7.000s 2335.142us 1 1 100.00
sec_cm_main_sm_ctr_local_esc 2 2 100.00
edn_alert 1.000s 29.035us 1 1 100.00
edn_sec_cm 7.000s 2335.142us 1 1 100.00
sec_cm_cs_rdata_bus_consistency 1 1 100.00
edn_alert 1.000s 29.035us 1 1 100.00
sec_cm_tile_link_bus_integrity 1 1 100.00
edn_tl_intg_err 9.000s 106.882us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 1 1 100.00
edn_stress_all_with_rand_reset 36.000s 1978.495us 1 1 100.00

Error Messages

   Test seed line log context
xmsim: *E,ASRTST (/nightly/current_run/scratch/master/edn_edn0-sim-xcelium/default/fusesoc-work/src/lowrisc_ip_edn_*/rtl/edn_ack_sm.sv,54): Assertion u_state_regs_A has failed
edn_err 98551053493177064238351807237697015117667859151523709879709284037158908114389 145
xmsim: *E,ASRTST (/nightly/current_run/scratch/master/edn_edn0-sim-xcelium/default/fusesoc-work/src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv,54): (time 1904754 PS) Assertion tb.dut.u_edn_core.gen_ep_blk[0].u_edn_ack_sm_ep.u_state_regs_A has failed
UVM_ERROR @ 1904754 ps: (edn_ack_sm.sv:54) [ASSERT FAILED] u_state_regs_A
UVM_INFO @ 1904754 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---