Simulation Results: hmac

 
02/04/2026 16:07:25 DVSim: v1.17.3 sha: 08f559e json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 73.70 %
  • code
  • 96.04 %
  • assert
  • 95.86 %
  • func
  • 29.21 %
  • block
  • 97.60 %
  • line
  • 98.39 %
  • branch
  • 93.99 %
  • toggle
  • 96.96 %
  • FSM
  • 94.83 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
V3
100.00%
unmapped
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
hmac_smoke 8.000s 3692.179us 1 1 100.00
csr_hw_reset 1 1 100.00
hmac_csr_hw_reset 2.000s 155.544us 1 1 100.00
csr_rw 1 1 100.00
hmac_csr_rw 1.000s 41.100us 1 1 100.00
csr_bit_bash 1 1 100.00
hmac_csr_bit_bash 5.000s 1992.907us 1 1 100.00
csr_aliasing 1 1 100.00
hmac_csr_aliasing 5.000s 2348.256us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
hmac_csr_mem_rw_with_rand_reset 3.000s 148.492us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
hmac_csr_rw 1.000s 41.100us 1 1 100.00
hmac_csr_aliasing 5.000s 2348.256us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
long_msg 1 1 100.00
hmac_long_msg 41.000s 4173.868us 1 1 100.00
back_pressure 1 1 100.00
hmac_back_pressure 19.000s 3389.167us 1 1 100.00
test_vectors 6 6 100.00
hmac_test_sha256_vectors 207.000s 5840.786us 1 1 100.00
hmac_test_sha384_vectors 22.000s 466.562us 1 1 100.00
hmac_test_sha512_vectors 21.000s 208.246us 1 1 100.00
hmac_test_hmac256_vectors 12.000s 1276.394us 1 1 100.00
hmac_test_hmac384_vectors 8.000s 243.013us 1 1 100.00
hmac_test_hmac512_vectors 15.000s 517.795us 1 1 100.00
burst_wr 1 1 100.00
hmac_burst_wr 16.000s 10455.372us 1 1 100.00
datapath_stress 1 1 100.00
hmac_datapath_stress 141.000s 12410.280us 1 1 100.00
error 1 1 100.00
hmac_error 103.000s 5084.907us 1 1 100.00
wipe_secret 1 1 100.00
hmac_wipe_secret 24.000s 1892.315us 1 1 100.00
save_and_restore 6 6 100.00
hmac_smoke 8.000s 3692.179us 1 1 100.00
hmac_long_msg 41.000s 4173.868us 1 1 100.00
hmac_back_pressure 19.000s 3389.167us 1 1 100.00
hmac_datapath_stress 141.000s 12410.280us 1 1 100.00
hmac_burst_wr 16.000s 10455.372us 1 1 100.00
hmac_stress_all 59.000s 6100.635us 1 1 100.00
fifo_empty_status_interrupt 11 11 100.00
hmac_smoke 8.000s 3692.179us 1 1 100.00
hmac_long_msg 41.000s 4173.868us 1 1 100.00
hmac_back_pressure 19.000s 3389.167us 1 1 100.00
hmac_datapath_stress 141.000s 12410.280us 1 1 100.00
hmac_wipe_secret 24.000s 1892.315us 1 1 100.00
hmac_test_sha256_vectors 207.000s 5840.786us 1 1 100.00
hmac_test_sha384_vectors 22.000s 466.562us 1 1 100.00
hmac_test_sha512_vectors 21.000s 208.246us 1 1 100.00
hmac_test_hmac256_vectors 12.000s 1276.394us 1 1 100.00
hmac_test_hmac384_vectors 8.000s 243.013us 1 1 100.00
hmac_test_hmac512_vectors 15.000s 517.795us 1 1 100.00
wide_digest_configurable_key_length 14 14 100.00
hmac_smoke 8.000s 3692.179us 1 1 100.00
hmac_long_msg 41.000s 4173.868us 1 1 100.00
hmac_back_pressure 19.000s 3389.167us 1 1 100.00
hmac_datapath_stress 141.000s 12410.280us 1 1 100.00
hmac_burst_wr 16.000s 10455.372us 1 1 100.00
hmac_error 103.000s 5084.907us 1 1 100.00
hmac_wipe_secret 24.000s 1892.315us 1 1 100.00
hmac_test_sha256_vectors 207.000s 5840.786us 1 1 100.00
hmac_test_sha384_vectors 22.000s 466.562us 1 1 100.00
hmac_test_sha512_vectors 21.000s 208.246us 1 1 100.00
hmac_test_hmac256_vectors 12.000s 1276.394us 1 1 100.00
hmac_test_hmac384_vectors 8.000s 243.013us 1 1 100.00
hmac_test_hmac512_vectors 15.000s 517.795us 1 1 100.00
hmac_stress_all 59.000s 6100.635us 1 1 100.00
stress_all 1 1 100.00
hmac_stress_all 59.000s 6100.635us 1 1 100.00
alert_test 1 1 100.00
hmac_alert_test 1.000s 18.070us 1 1 100.00
intr_test 1 1 100.00
hmac_intr_test 1.000s 13.674us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
hmac_tl_errors 3.000s 234.085us 1 1 100.00
tl_d_illegal_access 1 1 100.00
hmac_tl_errors 3.000s 234.085us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
hmac_csr_hw_reset 2.000s 155.544us 1 1 100.00
hmac_csr_rw 1.000s 41.100us 1 1 100.00
hmac_csr_aliasing 5.000s 2348.256us 1 1 100.00
hmac_same_csr_outstanding 2.000s 121.736us 1 1 100.00
tl_d_partial_access 4 4 100.00
hmac_csr_hw_reset 2.000s 155.544us 1 1 100.00
hmac_csr_rw 1.000s 41.100us 1 1 100.00
hmac_csr_aliasing 5.000s 2348.256us 1 1 100.00
hmac_same_csr_outstanding 2.000s 121.736us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
hmac_sec_cm 1.000s 237.435us 1 1 100.00
hmac_tl_intg_err 3.000s 165.054us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
hmac_tl_intg_err 3.000s 165.054us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
write_config_and_secret_key_during_msg_wr 1 1 100.00
hmac_smoke 8.000s 3692.179us 1 1 100.00
stress_reset 1 1 100.00
hmac_stress_reset 4.000s 59.674us 1 1 100.00
stress_all_with_rand_reset 1 1 100.00
hmac_stress_all_with_rand_reset 27.000s 8829.422us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
Unmapped 1 1 100.00
hmac_directed 3.000s 163.916us 1 1 100.00