Simulation Results: i2c

 
02/04/2026 16:07:25 DVSim: v1.17.3 sha: 08f559e json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 87.56 %
  • code
  • 89.25 %
  • assert
  • 93.02 %
  • func
  • 80.40 %
  • block
  • 95.95 %
  • line
  • 95.37 %
  • branch
  • 92.74 %
  • toggle
  • 86.90 %
  • FSM
  • 82.01 %
Validation stages
V1
100.00%
V2
85.37%
V2S
100.00%
V3
0.00%
Testpoint Test Max Runtime Sim Time Pass Total %
host_smoke 1 1 100.00
i2c_host_smoke 16.000s 958.566us 1 1 100.00
target_smoke 1 1 100.00
i2c_target_smoke 6.000s 2040.262us 1 1 100.00
csr_hw_reset 1 1 100.00
i2c_csr_hw_reset 1.000s 19.761us 1 1 100.00
csr_rw 1 1 100.00
i2c_csr_rw 1.000s 21.283us 1 1 100.00
csr_bit_bash 1 1 100.00
i2c_csr_bit_bash 2.000s 131.841us 1 1 100.00
csr_aliasing 1 1 100.00
i2c_csr_aliasing 2.000s 93.365us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
i2c_csr_mem_rw_with_rand_reset 1.000s 38.855us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
i2c_csr_rw 1.000s 21.283us 1 1 100.00
i2c_csr_aliasing 2.000s 93.365us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
host_error_intr 0 1 0.00
i2c_host_error_intr 3.000s 264.720us 0 1 0.00
host_stress_all 0 1 0.00
i2c_host_stress_all 0.000s 0.000us 0 1 0.00
host_maxperf 1 1 100.00
i2c_host_perf 261.000s 9623.975us 1 1 100.00
host_override 1 1 100.00
i2c_host_override 1.000s 16.500us 1 1 100.00
host_fifo_watermark 0 1 0.00
i2c_host_fifo_watermark 0.000s 0.000us 0 1 0.00
host_fifo_overflow 1 1 100.00
i2c_host_fifo_overflow 891.000s 22982.486us 1 1 100.00
host_fifo_reset 3 3 100.00
i2c_host_fifo_reset_fmt 1.000s 366.290us 1 1 100.00
i2c_host_fifo_fmt_empty 6.000s 197.822us 1 1 100.00
i2c_host_fifo_reset_rx 4.000s 230.279us 1 1 100.00
host_fifo_full 1 1 100.00
i2c_host_fifo_full 36.000s 9375.360us 1 1 100.00
host_timeout 1 1 100.00
i2c_host_stretch_timeout 9.000s 4573.285us 1 1 100.00
i2c_host_mode_toggle 1 1 100.00
i2c_host_mode_toggle 3.000s 117.506us 1 1 100.00
target_glitch 0 1 0.00
i2c_target_glitch 3.000s 941.733us 0 1 0.00
target_stress_all 1 1 100.00
i2c_target_stress_all 35.000s 32192.759us 1 1 100.00
target_maxperf 1 1 100.00
i2c_target_perf 4.000s 2354.232us 1 1 100.00
target_fifo_empty 2 2 100.00
i2c_target_stress_rd 45.000s 2807.049us 1 1 100.00
i2c_target_intr_smoke 6.000s 3688.328us 1 1 100.00
target_fifo_reset 2 2 100.00
i2c_target_fifo_reset_acq 2.000s 2562.176us 1 1 100.00
i2c_target_fifo_reset_tx 2.000s 735.184us 1 1 100.00
target_fifo_full 1 3 33.33
i2c_target_stress_wr 0.000s 0.000us 0 1 0.00
i2c_target_stress_rd 45.000s 2807.049us 1 1 100.00
i2c_target_intr_stress_wr 0.000s 0.000us 0 1 0.00
target_timeout 1 1 100.00
i2c_target_timeout 6.000s 4414.162us 1 1 100.00
target_clock_stretch 1 1 100.00
i2c_target_stretch 1280.000s 4749.876us 1 1 100.00
bad_address 1 1 100.00
i2c_target_bad_addr 6.000s 4615.837us 1 1 100.00
target_mode_glitch 1 1 100.00
i2c_target_hrst 3.000s 2031.492us 1 1 100.00
target_fifo_watermark 2 2 100.00
i2c_target_fifo_watermarks_acq 3.000s 1905.198us 1 1 100.00
i2c_target_fifo_watermarks_tx 1.000s 246.546us 1 1 100.00
host_mode_config_perf 2 2 100.00
i2c_host_perf 261.000s 9623.975us 1 1 100.00
i2c_host_perf_precise 4.000s 200.205us 1 1 100.00
host_mode_clock_stretching 1 1 100.00
i2c_host_stretch_timeout 9.000s 4573.285us 1 1 100.00
target_mode_tx_stretch_ctrl 1 1 100.00
i2c_target_tx_stretch_ctrl 2.000s 59.296us 1 1 100.00
target_mode_nack_generation 3 3 100.00
i2c_target_nack_acqfull 4.000s 1159.866us 1 1 100.00
i2c_target_nack_acqfull_addr 4.000s 2437.531us 1 1 100.00
i2c_target_nack_txstretch 2.000s 532.016us 1 1 100.00
host_mode_halt_on_nak 1 1 100.00
i2c_host_may_nack 15.000s 963.432us 1 1 100.00
target_mode_smbus_maxlen 1 1 100.00
i2c_target_smbus_maxlen 3.000s 861.768us 1 1 100.00
alert_test 1 1 100.00
i2c_alert_test 1.000s 14.522us 1 1 100.00
intr_test 1 1 100.00
i2c_intr_test 1.000s 97.100us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
i2c_tl_errors 2.000s 48.860us 1 1 100.00
tl_d_illegal_access 1 1 100.00
i2c_tl_errors 2.000s 48.860us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
i2c_csr_hw_reset 1.000s 19.761us 1 1 100.00
i2c_csr_rw 1.000s 21.283us 1 1 100.00
i2c_csr_aliasing 2.000s 93.365us 1 1 100.00
i2c_same_csr_outstanding 1.000s 77.073us 1 1 100.00
tl_d_partial_access 4 4 100.00
i2c_csr_hw_reset 1.000s 19.761us 1 1 100.00
i2c_csr_rw 1.000s 21.283us 1 1 100.00
i2c_csr_aliasing 2.000s 93.365us 1 1 100.00
i2c_same_csr_outstanding 1.000s 77.073us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
i2c_sec_cm 1.000s 73.914us 1 1 100.00
i2c_tl_intg_err 2.000s 179.540us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
i2c_tl_intg_err 2.000s 179.540us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
host_stress_all_with_rand_reset 0 1 0.00
i2c_host_stress_all_with_rand_reset 17.000s 1131.663us 0 1 0.00
target_error_intr 0 1 0.00
i2c_target_unexp_stop 3.000s 536.797us 0 1 0.00
target_stress_all_with_rand_reset 0 1 0.00
i2c_target_stress_all_with_rand_reset 2.000s 10.125us 0 1 0.00

Error Messages

   Test seed line log context
Job timed out after * minutes
i2c_host_fifo_watermark 57376621592650377097407291735969812453017645598925015310908817445931685209764 None
Job timed out after 60 minutes
i2c_host_stress_all 101599971438383473206160615352980821137811331612884371573112481771027672651836 None
Job timed out after 60 minutes
i2c_target_stress_wr 27988662412456365890792557050214234879496276709986019132206897978115793880984 None
Job timed out after 60 minutes
i2c_target_intr_stress_wr 18237864938541597479435977119238807504307928260566013488356963456181499601200 None
Job timed out after 60 minutes
UVM_ERROR sequencer [sequencer] Get_next_item called twice without item_done or get in between
i2c_host_error_intr 100419527143585834907555060242043930462966278884403431816438928918826955031441 100
UVM_ERROR @ 264719956 ps: uvm_test_top.env.m_i2c_agent.sequencer [uvm_test_top.env.m_i2c_agent.sequencer] Get_next_item called twice without item_done or get in between
UVM_INFO @ 264719956 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
i2c_target_stress_all_with_rand_reset 8768376300459015426620067270103093408417610034832520797921724902630051245989 94
UVM_ERROR @ 10124834 ps: uvm_test_top.env.m_i2c_agent.sequencer [uvm_test_top.env.m_i2c_agent.sequencer] Get_next_item called twice without item_done or get in between
UVM_INFO @ 10124834 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR sequencer [sequencer] get_next_item/try_next_item called twice without item_done or get in between
i2c_target_glitch 20665257305637735814689330019336765922389490658872856729276096824795576279918 93
UVM_ERROR @ 941733246 ps: uvm_test_top.env.m_i2c_agent.sequencer [uvm_test_top.env.m_i2c_agent.sequencer] get_next_item/try_next_item called twice without item_done or get in between
UVM_INFO @ 941733246 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (i2c_base_vseq.sv:1474) [i2c_target_ack_stop_vseq] Check failed obs_intr_state[intr] == exp_val (* [*] vs * [*])
i2c_target_unexp_stop 67188078755459915608958055861800095421751686460774155365001066578779825228106 87
UVM_ERROR @ 536797012 ps: (i2c_base_vseq.sv:1474) [uvm_test_top.env.virtual_sequencer.i2c_target_ack_stop_vseq] Check failed obs_intr_state[intr] == exp_val (0 [0x0] vs 1 [0x1])
UVM_INFO @ 536797012 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_vseq.sv:1237) [i2c_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses.
i2c_host_stress_all_with_rand_reset 3262030777490962558794848824524095400309368594575885167309255105666243992104 99
UVM_ERROR @ 1131662979 ps: (cip_base_vseq.sv:1237) [uvm_test_top.env.virtual_sequencer.i2c_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 1131662979 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---