| V1 |
|
100.00% |
| V2 |
|
100.00% |
| V2S |
|
90.91% |
| V3 |
|
0.00% |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| smoke | 1 | 1 | 100.00 | |||
| keymgr_smoke | 3.000s | 259.512us | 1 | 1 | 100.00 | |
| random | 1 | 1 | 100.00 | |||
| keymgr_random | 4.000s | 162.409us | 1 | 1 | 100.00 | |
| csr_hw_reset | 1 | 1 | 100.00 | |||
| keymgr_csr_hw_reset | 1.000s | 13.268us | 1 | 1 | 100.00 | |
| csr_rw | 1 | 1 | 100.00 | |||
| keymgr_csr_rw | 2.000s | 70.683us | 1 | 1 | 100.00 | |
| csr_bit_bash | 1 | 1 | 100.00 | |||
| keymgr_csr_bit_bash | 12.000s | 2610.959us | 1 | 1 | 100.00 | |
| csr_aliasing | 1 | 1 | 100.00 | |||
| keymgr_csr_aliasing | 5.000s | 127.300us | 1 | 1 | 100.00 | |
| csr_mem_rw_with_rand_reset | 1 | 1 | 100.00 | |||
| keymgr_csr_mem_rw_with_rand_reset | 2.000s | 29.963us | 1 | 1 | 100.00 | |
| regwen_csr_and_corresponding_lockable_csr | 2 | 2 | 100.00 | |||
| keymgr_csr_rw | 2.000s | 70.683us | 1 | 1 | 100.00 | |
| keymgr_csr_aliasing | 5.000s | 127.300us | 1 | 1 | 100.00 | |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| cfgen_during_op | 1 | 1 | 100.00 | |||
| keymgr_cfg_regwen | 58.000s | 3890.628us | 1 | 1 | 100.00 | |
| sideload | 4 | 4 | 100.00 | |||
| keymgr_sideload | 8.000s | 513.141us | 1 | 1 | 100.00 | |
| keymgr_sideload_kmac | 3.000s | 583.810us | 1 | 1 | 100.00 | |
| keymgr_sideload_aes | 3.000s | 182.855us | 1 | 1 | 100.00 | |
| keymgr_sideload_otbn | 8.000s | 2006.882us | 1 | 1 | 100.00 | |
| direct_to_disabled_state | 1 | 1 | 100.00 | |||
| keymgr_direct_to_disabled | 5.000s | 224.888us | 1 | 1 | 100.00 | |
| lc_disable | 1 | 1 | 100.00 | |||
| keymgr_lc_disable | 4.000s | 77.176us | 1 | 1 | 100.00 | |
| kmac_error_response | 1 | 1 | 100.00 | |||
| keymgr_kmac_rsp_err | 2.000s | 147.364us | 1 | 1 | 100.00 | |
| invalid_sw_input | 1 | 1 | 100.00 | |||
| keymgr_sw_invalid_input | 4.000s | 353.529us | 1 | 1 | 100.00 | |
| invalid_hw_input | 1 | 1 | 100.00 | |||
| keymgr_hwsw_invalid_input | 4.000s | 125.607us | 1 | 1 | 100.00 | |
| sync_async_fault_cross | 1 | 1 | 100.00 | |||
| keymgr_sync_async_fault_cross | 3.000s | 366.184us | 1 | 1 | 100.00 | |
| stress_all | 1 | 1 | 100.00 | |||
| keymgr_stress_all | 3.000s | 44.227us | 1 | 1 | 100.00 | |
| intr_test | 1 | 1 | 100.00 | |||
| keymgr_intr_test | 1.000s | 39.335us | 1 | 1 | 100.00 | |
| alert_test | 1 | 1 | 100.00 | |||
| keymgr_alert_test | 1.000s | 22.881us | 1 | 1 | 100.00 | |
| tl_d_oob_addr_access | 1 | 1 | 100.00 | |||
| keymgr_tl_errors | 3.000s | 122.110us | 1 | 1 | 100.00 | |
| tl_d_illegal_access | 1 | 1 | 100.00 | |||
| keymgr_tl_errors | 3.000s | 122.110us | 1 | 1 | 100.00 | |
| tl_d_outstanding_access | 4 | 4 | 100.00 | |||
| keymgr_csr_hw_reset | 1.000s | 13.268us | 1 | 1 | 100.00 | |
| keymgr_csr_rw | 2.000s | 70.683us | 1 | 1 | 100.00 | |
| keymgr_csr_aliasing | 5.000s | 127.300us | 1 | 1 | 100.00 | |
| keymgr_same_csr_outstanding | 2.000s | 83.786us | 1 | 1 | 100.00 | |
| tl_d_partial_access | 4 | 4 | 100.00 | |||
| keymgr_csr_hw_reset | 1.000s | 13.268us | 1 | 1 | 100.00 | |
| keymgr_csr_rw | 2.000s | 70.683us | 1 | 1 | 100.00 | |
| keymgr_csr_aliasing | 5.000s | 127.300us | 1 | 1 | 100.00 | |
| keymgr_same_csr_outstanding | 2.000s | 83.786us | 1 | 1 | 100.00 | |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| sec_cm_additional_check | 1 | 1 | 100.00 | |||
| keymgr_sec_cm | 5.000s | 469.362us | 1 | 1 | 100.00 | |
| tl_intg_err | 2 | 2 | 100.00 | |||
| keymgr_sec_cm | 5.000s | 469.362us | 1 | 1 | 100.00 | |
| keymgr_tl_intg_err | 4.000s | 397.021us | 1 | 1 | 100.00 | |
| shadow_reg_update_error | 1 | 1 | 100.00 | |||
| keymgr_shadow_reg_errors | 3.000s | 261.492us | 1 | 1 | 100.00 | |
| shadow_reg_read_clear_staged_value | 1 | 1 | 100.00 | |||
| keymgr_shadow_reg_errors | 3.000s | 261.492us | 1 | 1 | 100.00 | |
| shadow_reg_storage_error | 1 | 1 | 100.00 | |||
| keymgr_shadow_reg_errors | 3.000s | 261.492us | 1 | 1 | 100.00 | |
| shadowed_reset_glitch | 1 | 1 | 100.00 | |||
| keymgr_shadow_reg_errors | 3.000s | 261.492us | 1 | 1 | 100.00 | |
| shadow_reg_update_error_with_csr_rw | 1 | 1 | 100.00 | |||
| keymgr_shadow_reg_errors_with_csr_rw | 6.000s | 350.870us | 1 | 1 | 100.00 | |
| prim_count_check | 1 | 1 | 100.00 | |||
| keymgr_sec_cm | 5.000s | 469.362us | 1 | 1 | 100.00 | |
| prim_fsm_check | 1 | 1 | 100.00 | |||
| keymgr_sec_cm | 5.000s | 469.362us | 1 | 1 | 100.00 | |
| sec_cm_bus_integrity | 1 | 1 | 100.00 | |||
| keymgr_tl_intg_err | 4.000s | 397.021us | 1 | 1 | 100.00 | |
| sec_cm_config_shadow | 1 | 1 | 100.00 | |||
| keymgr_shadow_reg_errors | 3.000s | 261.492us | 1 | 1 | 100.00 | |
| sec_cm_op_config_regwen | 1 | 1 | 100.00 | |||
| keymgr_cfg_regwen | 58.000s | 3890.628us | 1 | 1 | 100.00 | |
| sec_cm_reseed_config_regwen | 2 | 2 | 100.00 | |||
| keymgr_random | 4.000s | 162.409us | 1 | 1 | 100.00 | |
| keymgr_csr_rw | 2.000s | 70.683us | 1 | 1 | 100.00 | |
| sec_cm_sw_binding_config_regwen | 2 | 2 | 100.00 | |||
| keymgr_random | 4.000s | 162.409us | 1 | 1 | 100.00 | |
| keymgr_csr_rw | 2.000s | 70.683us | 1 | 1 | 100.00 | |
| sec_cm_max_key_ver_config_regwen | 2 | 2 | 100.00 | |||
| keymgr_random | 4.000s | 162.409us | 1 | 1 | 100.00 | |
| keymgr_csr_rw | 2.000s | 70.683us | 1 | 1 | 100.00 | |
| sec_cm_lc_ctrl_intersig_mubi | 1 | 1 | 100.00 | |||
| keymgr_lc_disable | 4.000s | 77.176us | 1 | 1 | 100.00 | |
| sec_cm_constants_consistency | 1 | 1 | 100.00 | |||
| keymgr_hwsw_invalid_input | 4.000s | 125.607us | 1 | 1 | 100.00 | |
| sec_cm_intersig_consistency | 1 | 1 | 100.00 | |||
| keymgr_hwsw_invalid_input | 4.000s | 125.607us | 1 | 1 | 100.00 | |
| sec_cm_hw_key_sw_noaccess | 1 | 1 | 100.00 | |||
| keymgr_random | 4.000s | 162.409us | 1 | 1 | 100.00 | |
| sec_cm_output_keys_ctrl_redun | 1 | 1 | 100.00 | |||
| keymgr_sideload_protect | 3.000s | 89.267us | 1 | 1 | 100.00 | |
| sec_cm_ctrl_fsm_sparse | 1 | 1 | 100.00 | |||
| keymgr_sec_cm | 5.000s | 469.362us | 1 | 1 | 100.00 | |
| sec_cm_data_fsm_sparse | 1 | 1 | 100.00 | |||
| keymgr_sec_cm | 5.000s | 469.362us | 1 | 1 | 100.00 | |
| sec_cm_ctrl_fsm_local_esc | 1 | 1 | 100.00 | |||
| keymgr_sec_cm | 5.000s | 469.362us | 1 | 1 | 100.00 | |
| sec_cm_ctrl_fsm_consistency | 0 | 1 | 0.00 | |||
| keymgr_custom_cm | 1.000s | 0.000us | 0 | 1 | 0.00 | |
| sec_cm_ctrl_fsm_global_esc | 1 | 1 | 100.00 | |||
| keymgr_lc_disable | 4.000s | 77.176us | 1 | 1 | 100.00 | |
| sec_cm_ctrl_ctr_redun | 1 | 1 | 100.00 | |||
| keymgr_sec_cm | 5.000s | 469.362us | 1 | 1 | 100.00 | |
| sec_cm_kmac_if_fsm_sparse | 1 | 1 | 100.00 | |||
| keymgr_sec_cm | 5.000s | 469.362us | 1 | 1 | 100.00 | |
| sec_cm_kmac_if_ctr_redun | 1 | 1 | 100.00 | |||
| keymgr_sec_cm | 5.000s | 469.362us | 1 | 1 | 100.00 | |
| sec_cm_kmac_if_cmd_ctrl_consistency | 0 | 1 | 0.00 | |||
| keymgr_custom_cm | 1.000s | 0.000us | 0 | 1 | 0.00 | |
| sec_cm_kmac_if_done_ctrl_consistency | 0 | 1 | 0.00 | |||
| keymgr_custom_cm | 1.000s | 0.000us | 0 | 1 | 0.00 | |
| sec_cm_reseed_ctr_redun | 1 | 1 | 100.00 | |||
| keymgr_sec_cm | 5.000s | 469.362us | 1 | 1 | 100.00 | |
| sec_cm_side_load_sel_ctrl_consistency | 0 | 1 | 0.00 | |||
| keymgr_custom_cm | 1.000s | 0.000us | 0 | 1 | 0.00 | |
| sec_cm_sideload_ctrl_fsm_sparse | 1 | 1 | 100.00 | |||
| keymgr_sec_cm | 5.000s | 469.362us | 1 | 1 | 100.00 | |
| sec_cm_ctrl_key_integrity | 0 | 1 | 0.00 | |||
| keymgr_custom_cm | 1.000s | 0.000us | 0 | 1 | 0.00 | |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| stress_all_with_rand_reset | 0 | 1 | 0.00 | |||
| keymgr_stress_all_with_rand_reset | 5.000s | 575.792us | 0 | 1 | 0.00 | |
| Test | seed | line | log context | |
|---|---|---|---|---|
| Job returned non-zero exit code | ||||
| keymgr_custom_cm | 98890828301573673777614644341358282097103856036855321802592223074571060142115 | None |
|
xmsim: *W,SVRNDF (/nightly/current_run/scratch/master/keymgr-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_keymgr_env_0.1/seq_lib/keymgr_custom_cm_vseq.sv,13|21): The randomize method call failed. The unique id of the failed randomize call is 8.
Observed simulation time : 0 FS + 44.
xmsim: *F,RNDUNR: XCELIGEN assertion failed - 0
File - /dev/shm/avs_local_builds/avs_ramdisk_client_rifclx847/tbv/rnc/src/api/rnc_inside.cpp:1375, func - static rnc_node_sp rnc_node::new_inside_elt_node(const rnc_node_sp&, const rnc_node_sp&, rnc_sm)
Stacktrace:
0: rnc_assert_exception::rnc_assert_exception(char const*, int, char const*, char const*)
1: .
TOOL: xrun(64) 24.03-s007: Exiting on Apr 02, 2026 at 16:10:14 UTC (total: 00:00:01)
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:64: simulate] Error 2
|
|
| UVM_ERROR (cip_base_vseq.sv:1237) [keymgr_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. | ||||
| keymgr_stress_all_with_rand_reset | 92287548727583382308653990852502079493050883508384137036730673309475764484406 | 167 |
UVM_ERROR @ 575792102 ps: (cip_base_vseq.sv:1237) [uvm_test_top.env.virtual_sequencer.keymgr_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 575792102 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|