Simulation Results: lc_ctrl/volatile_unlock_disabled

 
02/04/2026 16:07:25 DVSim: v1.17.3 sha: 08f559e json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 91.64 %
  • code
  • 93.27 %
  • assert
  • 95.97 %
  • func
  • 85.67 %
  • block
  • 96.61 %
  • line
  • 97.29 %
  • branch
  • 91.38 %
  • toggle
  • 89.18 %
  • FSM
  • 95.24 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
lc_ctrl_smoke 3.000s 123.760us 1 1 100.00
csr_hw_reset 1 1 100.00
lc_ctrl_csr_hw_reset 2.000s 46.688us 1 1 100.00
csr_rw 1 1 100.00
lc_ctrl_csr_rw 2.000s 16.668us 1 1 100.00
csr_bit_bash 1 1 100.00
lc_ctrl_csr_bit_bash 3.000s 168.529us 1 1 100.00
csr_aliasing 1 1 100.00
lc_ctrl_csr_aliasing 2.000s 24.571us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
lc_ctrl_csr_mem_rw_with_rand_reset 1.000s 60.162us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
lc_ctrl_csr_rw 2.000s 16.668us 1 1 100.00
lc_ctrl_csr_aliasing 2.000s 24.571us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
state_post_trans 1 1 100.00
lc_ctrl_state_post_trans 4.000s 538.284us 1 1 100.00
regwen_during_op 1 1 100.00
lc_ctrl_regwen_during_op 6.000s 1723.500us 1 1 100.00
rand_wr_claim_transition_if 1 1 100.00
lc_ctrl_claim_transition_if 1.000s 106.284us 1 1 100.00
lc_prog_failure 1 1 100.00
lc_ctrl_prog_failure 3.000s 82.467us 1 1 100.00
lc_state_failure 1 1 100.00
lc_ctrl_state_failure 4.000s 610.764us 1 1 100.00
lc_errors 1 1 100.00
lc_ctrl_errors 8.000s 315.695us 1 1 100.00
security_escalation 7 7 100.00
lc_ctrl_state_failure 4.000s 610.764us 1 1 100.00
lc_ctrl_prog_failure 3.000s 82.467us 1 1 100.00
lc_ctrl_errors 8.000s 315.695us 1 1 100.00
lc_ctrl_security_escalation 6.000s 1698.840us 1 1 100.00
lc_ctrl_jtag_state_failure 27.000s 22618.900us 1 1 100.00
lc_ctrl_jtag_prog_failure 5.000s 371.188us 1 1 100.00
lc_ctrl_jtag_errors 14.000s 7146.525us 1 1 100.00
jtag_access 13 13 100.00
lc_ctrl_jtag_smoke 11.000s 1045.272us 1 1 100.00
lc_ctrl_jtag_state_post_trans 4.000s 836.733us 1 1 100.00
lc_ctrl_jtag_prog_failure 5.000s 371.188us 1 1 100.00
lc_ctrl_jtag_errors 14.000s 7146.525us 1 1 100.00
lc_ctrl_jtag_access 6.000s 1678.855us 1 1 100.00
lc_ctrl_jtag_regwen_during_op 8.000s 3077.139us 1 1 100.00
lc_ctrl_jtag_csr_hw_reset 2.000s 880.905us 1 1 100.00
lc_ctrl_jtag_csr_rw 2.000s 315.447us 1 1 100.00
lc_ctrl_jtag_csr_bit_bash 6.000s 2911.419us 1 1 100.00
lc_ctrl_jtag_csr_aliasing 4.000s 244.396us 1 1 100.00
lc_ctrl_jtag_same_csr_outstanding 2.000s 29.793us 1 1 100.00
lc_ctrl_jtag_csr_mem_rw_with_rand_reset 3.000s 396.650us 1 1 100.00
lc_ctrl_jtag_alert_test 2.000s 368.470us 1 1 100.00
jtag_priority 1 1 100.00
lc_ctrl_jtag_priority 2.000s 372.621us 1 1 100.00
lc_ctrl_volatile_unlock 1 1 100.00
lc_ctrl_volatile_unlock_smoke 2.000s 28.311us 1 1 100.00
stress_all 1 1 100.00
lc_ctrl_stress_all 36.000s 25847.382us 1 1 100.00
alert_test 1 1 100.00
lc_ctrl_alert_test 2.000s 16.706us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
lc_ctrl_tl_errors 3.000s 161.653us 1 1 100.00
tl_d_illegal_access 1 1 100.00
lc_ctrl_tl_errors 3.000s 161.653us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
lc_ctrl_csr_hw_reset 2.000s 46.688us 1 1 100.00
lc_ctrl_csr_rw 2.000s 16.668us 1 1 100.00
lc_ctrl_csr_aliasing 2.000s 24.571us 1 1 100.00
lc_ctrl_same_csr_outstanding 2.000s 116.813us 1 1 100.00
tl_d_partial_access 4 4 100.00
lc_ctrl_csr_hw_reset 2.000s 46.688us 1 1 100.00
lc_ctrl_csr_rw 2.000s 16.668us 1 1 100.00
lc_ctrl_csr_aliasing 2.000s 24.571us 1 1 100.00
lc_ctrl_same_csr_outstanding 2.000s 116.813us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
lc_ctrl_sec_cm 3.000s 492.306us 1 1 100.00
lc_ctrl_tl_intg_err 2.000s 342.595us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
lc_ctrl_tl_intg_err 2.000s 342.595us 1 1 100.00
sec_cm_transition_config_regwen 1 1 100.00
lc_ctrl_regwen_during_op 6.000s 1723.500us 1 1 100.00
sec_cm_manuf_state_sparse 2 2 100.00
lc_ctrl_state_failure 4.000s 610.764us 1 1 100.00
lc_ctrl_sec_cm 3.000s 492.306us 1 1 100.00
sec_cm_transition_ctr_sparse 2 2 100.00
lc_ctrl_state_failure 4.000s 610.764us 1 1 100.00
lc_ctrl_sec_cm 3.000s 492.306us 1 1 100.00
sec_cm_manuf_state_bkgn_chk 2 2 100.00
lc_ctrl_state_failure 4.000s 610.764us 1 1 100.00
lc_ctrl_sec_cm 3.000s 492.306us 1 1 100.00
sec_cm_transition_ctr_bkgn_chk 2 2 100.00
lc_ctrl_state_failure 4.000s 610.764us 1 1 100.00
lc_ctrl_sec_cm 3.000s 492.306us 1 1 100.00
sec_cm_state_config_sparse 2 2 100.00
lc_ctrl_state_failure 4.000s 610.764us 1 1 100.00
lc_ctrl_sec_cm 3.000s 492.306us 1 1 100.00
sec_cm_main_fsm_sparse 2 2 100.00
lc_ctrl_state_failure 4.000s 610.764us 1 1 100.00
lc_ctrl_sec_cm 3.000s 492.306us 1 1 100.00
sec_cm_kmac_fsm_sparse 2 2 100.00
lc_ctrl_state_failure 4.000s 610.764us 1 1 100.00
lc_ctrl_sec_cm 3.000s 492.306us 1 1 100.00
sec_cm_main_fsm_local_esc 2 2 100.00
lc_ctrl_state_failure 4.000s 610.764us 1 1 100.00
lc_ctrl_sec_cm 3.000s 492.306us 1 1 100.00
sec_cm_main_fsm_global_esc 1 1 100.00
lc_ctrl_security_escalation 6.000s 1698.840us 1 1 100.00
sec_cm_main_ctrl_flow_consistency 2 2 100.00
lc_ctrl_state_post_trans 4.000s 538.284us 1 1 100.00
lc_ctrl_jtag_state_post_trans 4.000s 836.733us 1 1 100.00
sec_cm_intersig_mubi 1 1 100.00
lc_ctrl_sec_mubi 6.000s 414.307us 1 1 100.00
sec_cm_token_valid_ctrl_mubi 1 1 100.00
lc_ctrl_sec_mubi 6.000s 414.307us 1 1 100.00
sec_cm_token_digest 1 1 100.00
lc_ctrl_sec_token_digest 7.000s 498.666us 1 1 100.00
sec_cm_token_mux_ctrl_redun 1 1 100.00
lc_ctrl_sec_token_mux 5.000s 424.943us 1 1 100.00
sec_cm_token_valid_mux_redun 1 1 100.00
lc_ctrl_sec_token_mux 5.000s 424.943us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 1 1 100.00
lc_ctrl_stress_all_with_rand_reset 25.000s 5511.032us 1 1 100.00