Simulation Results: lc_ctrl/volatile_unlock_enabled

 
02/04/2026 16:07:25 DVSim: v1.17.3 sha: 08f559e json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 92.33 %
  • code
  • 94.07 %
  • assert
  • 95.97 %
  • func
  • 86.94 %
  • block
  • 97.11 %
  • line
  • 97.66 %
  • branch
  • 92.68 %
  • toggle
  • 88.32 %
  • FSM
  • 97.62 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
lc_ctrl_smoke 2.000s 56.016us 1 1 100.00
csr_hw_reset 1 1 100.00
lc_ctrl_csr_hw_reset 2.000s 28.372us 1 1 100.00
csr_rw 1 1 100.00
lc_ctrl_csr_rw 2.000s 24.008us 1 1 100.00
csr_bit_bash 1 1 100.00
lc_ctrl_csr_bit_bash 3.000s 130.366us 1 1 100.00
csr_aliasing 1 1 100.00
lc_ctrl_csr_aliasing 1.000s 24.771us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
lc_ctrl_csr_mem_rw_with_rand_reset 1.000s 61.423us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
lc_ctrl_csr_rw 2.000s 24.008us 1 1 100.00
lc_ctrl_csr_aliasing 1.000s 24.771us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
state_post_trans 1 1 100.00
lc_ctrl_state_post_trans 3.000s 417.198us 1 1 100.00
regwen_during_op 1 1 100.00
lc_ctrl_regwen_during_op 11.000s 310.686us 1 1 100.00
rand_wr_claim_transition_if 1 1 100.00
lc_ctrl_claim_transition_if 1.000s 18.607us 1 1 100.00
lc_prog_failure 1 1 100.00
lc_ctrl_prog_failure 3.000s 183.428us 1 1 100.00
lc_state_failure 1 1 100.00
lc_ctrl_state_failure 5.000s 928.439us 1 1 100.00
lc_errors 1 1 100.00
lc_ctrl_errors 5.000s 295.518us 1 1 100.00
security_escalation 7 7 100.00
lc_ctrl_state_failure 5.000s 928.439us 1 1 100.00
lc_ctrl_prog_failure 3.000s 183.428us 1 1 100.00
lc_ctrl_errors 5.000s 295.518us 1 1 100.00
lc_ctrl_security_escalation 5.000s 958.663us 1 1 100.00
lc_ctrl_jtag_state_failure 22.000s 38587.736us 1 1 100.00
lc_ctrl_jtag_prog_failure 7.000s 4120.564us 1 1 100.00
lc_ctrl_jtag_errors 25.000s 6275.575us 1 1 100.00
jtag_access 13 13 100.00
lc_ctrl_jtag_smoke 3.000s 102.892us 1 1 100.00
lc_ctrl_jtag_state_post_trans 5.000s 1220.077us 1 1 100.00
lc_ctrl_jtag_prog_failure 7.000s 4120.564us 1 1 100.00
lc_ctrl_jtag_errors 25.000s 6275.575us 1 1 100.00
lc_ctrl_jtag_access 5.000s 4301.064us 1 1 100.00
lc_ctrl_jtag_regwen_during_op 18.000s 1280.848us 1 1 100.00
lc_ctrl_jtag_csr_hw_reset 2.000s 51.482us 1 1 100.00
lc_ctrl_jtag_csr_rw 2.000s 241.744us 1 1 100.00
lc_ctrl_jtag_csr_bit_bash 12.000s 754.164us 1 1 100.00
lc_ctrl_jtag_csr_aliasing 3.000s 321.804us 1 1 100.00
lc_ctrl_jtag_same_csr_outstanding 2.000s 106.956us 1 1 100.00
lc_ctrl_jtag_csr_mem_rw_with_rand_reset 1.000s 334.007us 1 1 100.00
lc_ctrl_jtag_alert_test 3.000s 444.436us 1 1 100.00
jtag_priority 1 1 100.00
lc_ctrl_jtag_priority 3.000s 160.419us 1 1 100.00
lc_ctrl_volatile_unlock 1 1 100.00
lc_ctrl_volatile_unlock_smoke 2.000s 13.774us 1 1 100.00
stress_all 1 1 100.00
lc_ctrl_stress_all 62.000s 24715.998us 1 1 100.00
alert_test 1 1 100.00
lc_ctrl_alert_test 1.000s 71.979us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
lc_ctrl_tl_errors 2.000s 114.664us 1 1 100.00
tl_d_illegal_access 1 1 100.00
lc_ctrl_tl_errors 2.000s 114.664us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
lc_ctrl_csr_hw_reset 2.000s 28.372us 1 1 100.00
lc_ctrl_csr_rw 2.000s 24.008us 1 1 100.00
lc_ctrl_csr_aliasing 1.000s 24.771us 1 1 100.00
lc_ctrl_same_csr_outstanding 2.000s 337.149us 1 1 100.00
tl_d_partial_access 4 4 100.00
lc_ctrl_csr_hw_reset 2.000s 28.372us 1 1 100.00
lc_ctrl_csr_rw 2.000s 24.008us 1 1 100.00
lc_ctrl_csr_aliasing 1.000s 24.771us 1 1 100.00
lc_ctrl_same_csr_outstanding 2.000s 337.149us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
lc_ctrl_sec_cm 4.000s 502.399us 1 1 100.00
lc_ctrl_tl_intg_err 2.000s 61.069us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
lc_ctrl_tl_intg_err 2.000s 61.069us 1 1 100.00
sec_cm_transition_config_regwen 1 1 100.00
lc_ctrl_regwen_during_op 11.000s 310.686us 1 1 100.00
sec_cm_manuf_state_sparse 2 2 100.00
lc_ctrl_state_failure 5.000s 928.439us 1 1 100.00
lc_ctrl_sec_cm 4.000s 502.399us 1 1 100.00
sec_cm_transition_ctr_sparse 2 2 100.00
lc_ctrl_state_failure 5.000s 928.439us 1 1 100.00
lc_ctrl_sec_cm 4.000s 502.399us 1 1 100.00
sec_cm_manuf_state_bkgn_chk 2 2 100.00
lc_ctrl_state_failure 5.000s 928.439us 1 1 100.00
lc_ctrl_sec_cm 4.000s 502.399us 1 1 100.00
sec_cm_transition_ctr_bkgn_chk 2 2 100.00
lc_ctrl_state_failure 5.000s 928.439us 1 1 100.00
lc_ctrl_sec_cm 4.000s 502.399us 1 1 100.00
sec_cm_state_config_sparse 2 2 100.00
lc_ctrl_state_failure 5.000s 928.439us 1 1 100.00
lc_ctrl_sec_cm 4.000s 502.399us 1 1 100.00
sec_cm_main_fsm_sparse 2 2 100.00
lc_ctrl_state_failure 5.000s 928.439us 1 1 100.00
lc_ctrl_sec_cm 4.000s 502.399us 1 1 100.00
sec_cm_kmac_fsm_sparse 2 2 100.00
lc_ctrl_state_failure 5.000s 928.439us 1 1 100.00
lc_ctrl_sec_cm 4.000s 502.399us 1 1 100.00
sec_cm_main_fsm_local_esc 2 2 100.00
lc_ctrl_state_failure 5.000s 928.439us 1 1 100.00
lc_ctrl_sec_cm 4.000s 502.399us 1 1 100.00
sec_cm_main_fsm_global_esc 1 1 100.00
lc_ctrl_security_escalation 5.000s 958.663us 1 1 100.00
sec_cm_main_ctrl_flow_consistency 2 2 100.00
lc_ctrl_state_post_trans 3.000s 417.198us 1 1 100.00
lc_ctrl_jtag_state_post_trans 5.000s 1220.077us 1 1 100.00
sec_cm_intersig_mubi 1 1 100.00
lc_ctrl_sec_mubi 5.000s 324.859us 1 1 100.00
sec_cm_token_valid_ctrl_mubi 1 1 100.00
lc_ctrl_sec_mubi 5.000s 324.859us 1 1 100.00
sec_cm_token_digest 1 1 100.00
lc_ctrl_sec_token_digest 6.000s 919.677us 1 1 100.00
sec_cm_token_mux_ctrl_redun 1 1 100.00
lc_ctrl_sec_token_mux 3.000s 482.577us 1 1 100.00
sec_cm_token_valid_mux_redun 1 1 100.00
lc_ctrl_sec_token_mux 3.000s 482.577us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 1 1 100.00
lc_ctrl_stress_all_with_rand_reset 58.000s 15657.563us 1 1 100.00