Simulation Results: otbn

 
02/04/2026 16:07:25 DVSim: v1.17.3 sha: 08f559e json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 94.05 %
  • code
  • 95.19 %
  • assert
  • 89.50 %
  • func
  • 97.46 %
  • block
  • 99.39 %
  • line
  • 99.58 %
  • branch
  • 92.22 %
  • toggle
  • 91.51 %
  • FSM
  • 97.44 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
V3
0.00%
unmapped
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
otbn_smoke 9.000s 130.585us 1 1 100.00
single_binary 1 1 100.00
otbn_single 9.000s 115.612us 1 1 100.00
csr_hw_reset 1 1 100.00
otbn_csr_hw_reset 3.000s 30.667us 1 1 100.00
csr_rw 1 1 100.00
otbn_csr_rw 5.000s 21.644us 1 1 100.00
csr_bit_bash 1 1 100.00
otbn_csr_bit_bash 6.000s 646.673us 1 1 100.00
csr_aliasing 1 1 100.00
otbn_csr_aliasing 4.000s 12.260us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
otbn_csr_mem_rw_with_rand_reset 6.000s 90.061us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
otbn_csr_rw 5.000s 21.644us 1 1 100.00
otbn_csr_aliasing 4.000s 12.260us 1 1 100.00
mem_walk 1 1 100.00
otbn_mem_walk 58.000s 4127.682us 1 1 100.00
mem_partial_access 1 1 100.00
otbn_mem_partial_access 24.000s 335.195us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
reset_recovery 1 1 100.00
otbn_reset 25.000s 429.042us 1 1 100.00
multi_error 1 1 100.00
otbn_multi_err 39.000s 316.948us 1 1 100.00
back_to_back 1 1 100.00
otbn_multi 41.000s 112.038us 1 1 100.00
stress_all 1 1 100.00
otbn_stress_all 30.000s 218.712us 1 1 100.00
lc_escalation 1 1 100.00
otbn_escalate 8.000s 344.371us 1 1 100.00
zero_state_err_urnd 1 1 100.00
otbn_zero_state_err_urnd 5.000s 125.774us 1 1 100.00
sw_errs_fatal_chk 1 1 100.00
otbn_sw_errs_fatal_chk 10.000s 38.097us 1 1 100.00
alert_test 1 1 100.00
otbn_alert_test 5.000s 113.986us 1 1 100.00
intr_test 1 1 100.00
otbn_intr_test 3.000s 55.944us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
otbn_tl_errors 4.000s 134.702us 1 1 100.00
tl_d_illegal_access 1 1 100.00
otbn_tl_errors 4.000s 134.702us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
otbn_csr_hw_reset 3.000s 30.667us 1 1 100.00
otbn_csr_rw 5.000s 21.644us 1 1 100.00
otbn_csr_aliasing 4.000s 12.260us 1 1 100.00
otbn_same_csr_outstanding 3.000s 99.849us 1 1 100.00
tl_d_partial_access 4 4 100.00
otbn_csr_hw_reset 3.000s 30.667us 1 1 100.00
otbn_csr_rw 5.000s 21.644us 1 1 100.00
otbn_csr_aliasing 4.000s 12.260us 1 1 100.00
otbn_same_csr_outstanding 3.000s 99.849us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
mem_integrity 2 2 100.00
otbn_imem_err 16.000s 113.688us 1 1 100.00
otbn_dmem_err 11.000s 63.093us 1 1 100.00
internal_integrity 4 4 100.00
otbn_alu_bignum_mod_err 9.000s 118.572us 1 1 100.00
otbn_controller_ispr_rdata_err 7.000s 13.382us 1 1 100.00
otbn_mac_bignum_acc_err 6.000s 190.185us 1 1 100.00
otbn_urnd_err 4.000s 16.966us 1 1 100.00
illegal_bus_access 1 1 100.00
otbn_illegal_mem_acc 5.000s 21.237us 1 1 100.00
otbn_mem_gnt_acc_err 1 1 100.00
otbn_mem_gnt_acc_err 6.000s 12.788us 1 1 100.00
otbn_non_sec_partial_wipe 1 1 100.00
otbn_partial_wipe 6.000s 55.980us 1 1 100.00
tl_intg_err 2 2 100.00
otbn_sec_cm 192.000s 4204.877us 1 1 100.00
otbn_tl_intg_err 18.000s 217.748us 1 1 100.00
passthru_mem_tl_intg_err 1 1 100.00
otbn_passthru_mem_tl_intg_err 22.000s 209.927us 1 1 100.00
prim_fsm_check 1 1 100.00
otbn_sec_cm 192.000s 4204.877us 1 1 100.00
prim_count_check 1 1 100.00
otbn_sec_cm 192.000s 4204.877us 1 1 100.00
sec_cm_mem_scramble 1 1 100.00
otbn_smoke 9.000s 130.585us 1 1 100.00
sec_cm_data_mem_integrity 1 1 100.00
otbn_dmem_err 11.000s 63.093us 1 1 100.00
sec_cm_instruction_mem_integrity 1 1 100.00
otbn_imem_err 16.000s 113.688us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
otbn_tl_intg_err 18.000s 217.748us 1 1 100.00
sec_cm_controller_fsm_global_esc 1 1 100.00
otbn_escalate 8.000s 344.371us 1 1 100.00
sec_cm_controller_fsm_local_esc 5 5 100.00
otbn_imem_err 16.000s 113.688us 1 1 100.00
otbn_dmem_err 11.000s 63.093us 1 1 100.00
otbn_zero_state_err_urnd 5.000s 125.774us 1 1 100.00
otbn_illegal_mem_acc 5.000s 21.237us 1 1 100.00
otbn_sec_cm 192.000s 4204.877us 1 1 100.00
sec_cm_controller_fsm_sparse 1 1 100.00
otbn_sec_cm 192.000s 4204.877us 1 1 100.00
sec_cm_scramble_key_sideload 1 1 100.00
otbn_single 9.000s 115.612us 1 1 100.00
sec_cm_scramble_ctrl_fsm_local_esc 5 5 100.00
otbn_imem_err 16.000s 113.688us 1 1 100.00
otbn_dmem_err 11.000s 63.093us 1 1 100.00
otbn_zero_state_err_urnd 5.000s 125.774us 1 1 100.00
otbn_illegal_mem_acc 5.000s 21.237us 1 1 100.00
otbn_sec_cm 192.000s 4204.877us 1 1 100.00
sec_cm_scramble_ctrl_fsm_sparse 1 1 100.00
otbn_sec_cm 192.000s 4204.877us 1 1 100.00
sec_cm_start_stop_ctrl_fsm_global_esc 1 1 100.00
otbn_escalate 8.000s 344.371us 1 1 100.00
sec_cm_start_stop_ctrl_fsm_local_esc 5 5 100.00
otbn_imem_err 16.000s 113.688us 1 1 100.00
otbn_dmem_err 11.000s 63.093us 1 1 100.00
otbn_zero_state_err_urnd 5.000s 125.774us 1 1 100.00
otbn_illegal_mem_acc 5.000s 21.237us 1 1 100.00
otbn_sec_cm 192.000s 4204.877us 1 1 100.00
sec_cm_start_stop_ctrl_fsm_sparse 1 1 100.00
otbn_sec_cm 192.000s 4204.877us 1 1 100.00
sec_cm_data_reg_sw_sca 1 1 100.00
otbn_single 9.000s 115.612us 1 1 100.00
sec_cm_ctrl_redun 1 1 100.00
otbn_ctrl_redun 7.000s 16.977us 1 1 100.00
sec_cm_pc_ctrl_flow_redun 1 1 100.00
otbn_pc_ctrl_flow_redun 5.000s 38.159us 1 1 100.00
sec_cm_rnd_bus_consistency 1 1 100.00
otbn_rnd_sec_cm 40.000s 1290.650us 1 1 100.00
sec_cm_rnd_rng_digest 1 1 100.00
otbn_rnd_sec_cm 40.000s 1290.650us 1 1 100.00
sec_cm_rf_base_data_reg_sw_integrity 1 1 100.00
otbn_rf_base_intg_err 7.000s 57.611us 1 1 100.00
sec_cm_rf_base_data_reg_sw_glitch_detect 1 1 100.00
otbn_sec_cm 192.000s 4204.877us 1 1 100.00
sec_cm_stack_wr_ptr_ctr_redun 1 1 100.00
otbn_sec_cm 192.000s 4204.877us 1 1 100.00
sec_cm_rf_bignum_data_reg_sw_integrity 1 1 100.00
otbn_rf_bignum_intg_err 7.000s 54.096us 1 1 100.00
sec_cm_rf_bignum_data_reg_sw_glitch_detect 1 1 100.00
otbn_sec_cm 192.000s 4204.877us 1 1 100.00
sec_cm_loop_stack_ctr_redun 1 1 100.00
otbn_sec_cm 192.000s 4204.877us 1 1 100.00
sec_cm_loop_stack_addr_integrity 1 1 100.00
otbn_stack_addr_integ_chk 7.000s 26.885us 1 1 100.00
sec_cm_call_stack_addr_integrity 1 1 100.00
otbn_stack_addr_integ_chk 7.000s 26.885us 1 1 100.00
sec_cm_start_stop_ctrl_state_consistency 1 1 100.00
otbn_sec_wipe_err 5.000s 16.489us 1 1 100.00
sec_cm_data_mem_sec_wipe 1 1 100.00
otbn_single 9.000s 115.612us 1 1 100.00
sec_cm_instruction_mem_sec_wipe 1 1 100.00
otbn_single 9.000s 115.612us 1 1 100.00
sec_cm_data_reg_sw_sec_wipe 1 1 100.00
otbn_single 9.000s 115.612us 1 1 100.00
sec_cm_write_mem_integrity 1 1 100.00
otbn_multi 41.000s 112.038us 1 1 100.00
sec_cm_ctrl_flow_count 1 1 100.00
otbn_single 9.000s 115.612us 1 1 100.00
sec_cm_ctrl_flow_sca 1 1 100.00
otbn_single 9.000s 115.612us 1 1 100.00
sec_cm_data_mem_sw_noaccess 1 1 100.00
otbn_sw_no_acc 10.000s 37.392us 1 1 100.00
sec_cm_key_sideload 1 1 100.00
otbn_single 9.000s 115.612us 1 1 100.00
sec_cm_tlul_fifo_ctr_redun 1 1 100.00
otbn_sec_cm 192.000s 4204.877us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 0 1 0.00
otbn_stress_all_with_rand_reset 44.000s 234.901us 0 1 0.00
Testpoint Test Max Runtime Sim Time Pass Total %
Unmapped 1 1 100.00
otbn_smoke_vectorized 6.000s 36.555us 1 1 100.00

Error Messages

   Test seed line log context
UVM_ERROR (cip_base_vseq.sv:1237) [otbn_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses.
otbn_stress_all_with_rand_reset 57886987962584520869554504298954328363712575770388373840967987698012880059949 167
UVM_ERROR @ 234900720 ps: (cip_base_vseq.sv:1237) [uvm_test_top.env.virtual_sequencer.otbn_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 234900720 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---