Simulation Results: rv_dm/use_dmi_interface

 
02/04/2026 16:07:25 DVSim: v1.17.3 sha: 08f559e json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 88.06 %
  • code
  • 75.13 %
  • assert
  • 96.20 %
  • func
  • 92.86 %
  • block
  • 89.69 %
  • line
  • 89.47 %
  • branch
  • 72.02 %
  • toggle
  • 76.52 %
  • FSM
  • 62.50 %
Validation stages
V1
96.30%
V2
69.57%
V2S
100.00%
V3
0.00%
unmapped
0.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
rv_dm_smoke 32.000s 951.888us 1 1 100.00
jtag_dtm_csr_hw_reset 1 1 100.00
rv_dm_jtag_dtm_csr_hw_reset 29.000s 977.924us 1 1 100.00
jtag_dtm_csr_rw 1 1 100.00
rv_dm_jtag_dtm_csr_rw 29.000s 1081.179us 1 1 100.00
jtag_dtm_csr_bit_bash 1 1 100.00
rv_dm_jtag_dtm_csr_bit_bash 43.000s 10413.653us 1 1 100.00
jtag_dtm_csr_aliasing 1 1 100.00
rv_dm_jtag_dtm_csr_aliasing 29.000s 537.252us 1 1 100.00
jtag_dmi_csr_hw_reset 1 1 100.00
rv_dm_jtag_dmi_csr_hw_reset 37.000s 13876.901us 1 1 100.00
jtag_dmi_csr_rw 1 1 100.00
rv_dm_jtag_dmi_csr_rw 31.000s 2198.563us 1 1 100.00
jtag_dmi_csr_bit_bash 1 1 100.00
rv_dm_jtag_dmi_csr_bit_bash 33.000s 12027.967us 1 1 100.00
jtag_dmi_csr_aliasing 1 1 100.00
rv_dm_jtag_dmi_csr_aliasing 46.000s 48249.099us 1 1 100.00
jtag_dmi_cmderr_busy 1 1 100.00
rv_dm_cmderr_busy 35.000s 300.276us 1 1 100.00
jtag_dmi_cmderr_not_supported 1 1 100.00
rv_dm_cmderr_not_supported 31.000s 682.715us 1 1 100.00
cmderr_exception 1 1 100.00
rv_dm_cmderr_exception 31.000s 403.694us 1 1 100.00
mem_tl_access_resuming 0 1 0.00
rv_dm_mem_tl_access_resuming 31.000s 297.653us 0 1 0.00
mem_tl_access_halted 1 1 100.00
rv_dm_mem_tl_access_halted 32.000s 177.805us 1 1 100.00
cmderr_halt_resume 1 1 100.00
rv_dm_cmderr_halt_resume 34.000s 1425.001us 1 1 100.00
dataaddr_rw_access 1 1 100.00
rv_dm_dataaddr_rw_access 32.000s 421.895us 1 1 100.00
halt_resume 1 1 100.00
rv_dm_halt_resume_whereto 33.000s 564.762us 1 1 100.00
progbuf_busy 1 1 100.00
rv_dm_cmderr_busy 35.000s 300.276us 1 1 100.00
abstractcmd_status 1 1 100.00
rv_dm_abstractcmd_status 34.000s 217.709us 1 1 100.00
progbuf_read_write_execute 1 1 100.00
rv_dm_progbuf_read_write_execute 33.000s 657.071us 1 1 100.00
progbuf_exception 1 1 100.00
rv_dm_cmderr_exception 31.000s 403.694us 1 1 100.00
rom_read_access 1 1 100.00
rv_dm_rom_read_access 33.000s 77.908us 1 1 100.00
csr_hw_reset 1 1 100.00
rv_dm_csr_hw_reset 30.000s 142.050us 1 1 100.00
csr_rw 1 1 100.00
rv_dm_csr_rw 29.000s 98.748us 1 1 100.00
csr_bit_bash 1 1 100.00
rv_dm_csr_bit_bash 46.000s 9851.338us 1 1 100.00
csr_aliasing 1 1 100.00
rv_dm_csr_aliasing 56.000s 2398.883us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
rv_dm_csr_mem_rw_with_rand_reset 30.000s 144.391us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
rv_dm_csr_aliasing 56.000s 2398.883us 1 1 100.00
rv_dm_csr_rw 29.000s 98.748us 1 1 100.00
mem_walk 1 1 100.00
rv_dm_mem_walk 28.000s 139.309us 1 1 100.00
mem_partial_access 1 1 100.00
rv_dm_mem_partial_access 28.000s 114.442us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
idcode 1 1 100.00
rv_dm_smoke 32.000s 951.888us 1 1 100.00
jtag_dtm_hard_reset 1 1 100.00
rv_dm_jtag_dtm_hard_reset 32.000s 215.464us 1 1 100.00
jtag_dtm_idle_hint 1 1 100.00
rv_dm_jtag_dtm_idle_hint 34.000s 799.391us 1 1 100.00
jtag_dmi_failed_op 1 1 100.00
rv_dm_dmi_failed_op 34.000s 319.350us 1 1 100.00
jtag_dmi_dm_inactive 1 1 100.00
rv_dm_jtag_dmi_dm_inactive 35.000s 1748.432us 1 1 100.00
sba 0 2 0.00
rv_dm_sba_tl_access 569.000s 300000.000us 0 1 0.00
rv_dm_delayed_resp_sba_tl_access 327.000s 300000.000us 0 1 0.00
bad_sba 0 1 0.00
rv_dm_bad_sba_tl_access 428.000s 300000.000us 0 1 0.00
sba_autoincrement 0 1 0.00
rv_dm_autoincr_sba_tl_access 523.000s 300000.000us 0 1 0.00
jtag_dmi_debug_disabled 0 1 0.00
rv_dm_jtag_dmi_debug_disabled 36.000s 232.493us 0 1 0.00
sba_debug_disabled 1 1 100.00
rv_dm_sba_debug_disabled 40.000s 1809.839us 1 1 100.00
ndmreset_req 1 1 100.00
rv_dm_ndmreset_req 32.000s 376.786us 1 1 100.00
hart_unavail 0 1 0.00
rv_dm_hart_unavail 30.000s 279.443us 0 1 0.00
tap_ctrl_transitions 2 2 100.00
rv_dm_tap_fsm_rand_reset 68.000s 61333.457us 1 1 100.00
rv_dm_tap_fsm 38.000s 11967.320us 1 1 100.00
hartsel_warl 1 1 100.00
rv_dm_hartsel_warl 33.000s 70.643us 1 1 100.00
stress_all 0 1 0.00
rv_dm_stress_all 0.000s 0.000us 0 1 0.00
alert_test 1 1 100.00
rv_dm_alert_test 31.000s 30.272us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
rv_dm_tl_errors 31.000s 480.103us 1 1 100.00
tl_d_illegal_access 1 1 100.00
rv_dm_tl_errors 31.000s 480.103us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
rv_dm_csr_aliasing 56.000s 2398.883us 1 1 100.00
rv_dm_csr_hw_reset 30.000s 142.050us 1 1 100.00
rv_dm_csr_rw 29.000s 98.748us 1 1 100.00
rv_dm_same_csr_outstanding 31.000s 641.241us 1 1 100.00
tl_d_partial_access 4 4 100.00
rv_dm_csr_aliasing 56.000s 2398.883us 1 1 100.00
rv_dm_csr_hw_reset 30.000s 142.050us 1 1 100.00
rv_dm_csr_rw 29.000s 98.748us 1 1 100.00
rv_dm_same_csr_outstanding 31.000s 641.241us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
rv_dm_tl_intg_err 40.000s 6840.246us 1 1 100.00
rv_dm_sec_cm 32.000s 1295.458us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
rv_dm_tl_intg_err 40.000s 6840.246us 1 1 100.00
sec_cm_lc_hw_debug_en_intersig_mubi 2 2 100.00
rv_dm_sba_debug_disabled 40.000s 1809.839us 1 1 100.00
rv_dm_debug_disabled 34.000s 122.037us 1 1 100.00
sec_cm_lc_dft_en_intersig_mubi 2 2 100.00
rv_dm_sba_debug_disabled 40.000s 1809.839us 1 1 100.00
rv_dm_debug_disabled 34.000s 122.037us 1 1 100.00
sec_cm_otp_dis_rv_dm_late_debug_intersig_mubi 1 1 100.00
rv_dm_smoke 32.000s 951.888us 1 1 100.00
sec_cm_dm_en_ctrl_lc_gated 1 1 100.00
rv_dm_buffered_enable 31.000s 140.449us 1 1 100.00
sec_cm_sba_tl_lc_gate_fsm_sparse 1 1 100.00
rv_dm_sparse_lc_gate_fsm 31.000s 90.879us 1 1 100.00
sec_cm_mem_tl_lc_gate_fsm_sparse 1 1 100.00
rv_dm_sparse_lc_gate_fsm 31.000s 90.879us 1 1 100.00
sec_cm_exec_ctrl_mubi 1 1 100.00
rv_dm_buffered_enable 31.000s 140.449us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 0 1 0.00
rv_dm_stress_all_with_rand_reset 42.000s 3347.544us 0 1 0.00
Testpoint Test Max Runtime Sim Time Pass Total %
Unmapped 0 1 0.00
rv_dm_scanmode 292.000s 300000.000us 0 1 0.00

Error Messages

   Test seed line log context
UVM_FATAL (uvm_phase.svh:1521) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue
rv_dm_sba_tl_access 22755834407545787088594933038821609608473936102739057715313299097566935953254 87
UVM_FATAL @ 300000000000 ps: (uvm_phase.svh:1521) [PH_TIMEOUT] Explicit timeout of 300000000000 ps hit, indicating a probable testbench issue
UVM_INFO @ 300000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rv_dm_delayed_resp_sba_tl_access 17277673760350830059990070540161773603326191046905694593458719991296131368574 87
UVM_FATAL @ 300000000000 ps: (uvm_phase.svh:1521) [PH_TIMEOUT] Explicit timeout of 300000000000 ps hit, indicating a probable testbench issue
UVM_INFO @ 300000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rv_dm_bad_sba_tl_access 44958284185818708373074441242536906716461794903322003921863056079489541738889 87
UVM_FATAL @ 300000000000 ps: (uvm_phase.svh:1521) [PH_TIMEOUT] Explicit timeout of 300000000000 ps hit, indicating a probable testbench issue
UVM_INFO @ 300000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rv_dm_autoincr_sba_tl_access 40588942300666406437120263102803445789833418354695600910113329801907883158080 87
UVM_FATAL @ 300000000000 ps: (uvm_phase.svh:1521) [PH_TIMEOUT] Explicit timeout of 300000000000 ps hit, indicating a probable testbench issue
UVM_INFO @ 300000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rv_dm_scanmode 10379990840535377429625996028123065886352959767239587067859963164862672125098 87
UVM_FATAL @ 300000000000 ps: (uvm_phase.svh:1521) [PH_TIMEOUT] Explicit timeout of 300000000000 ps hit, indicating a probable testbench issue
UVM_INFO @ 300000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (rv_dm_mem_tl_access_resuming_vseq.sv:56) [rv_dm_mem_tl_access_resuming_vseq] Check failed jtag_dmi_ral.dmstatus.anyhalted.get_mirrored_value() == *'b* (* [*] vs * [*])
rv_dm_mem_tl_access_resuming 71231703079399441427248028129047153859063566364407250687131268437538509316998 87
UVM_ERROR @ 297653445 ps: (rv_dm_mem_tl_access_resuming_vseq.sv:56) [uvm_test_top.env.virtual_sequencer.rv_dm_mem_tl_access_resuming_vseq] Check failed jtag_dmi_ral.dmstatus.anyhalted.get_mirrored_value() == 1'b1 (0 [0x0] vs 1 [0x1])
UVM_INFO @ 297653445 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (rv_dm_hart_unavail_vseq.sv:24) [rv_dm_hart_unavail_vseq] Check failed jtag_dmi_ral.dmstatus.anyunavail.get_mirrored_value() == req_unavailable (* [*] vs * [*])
rv_dm_hart_unavail 93703673381190009212822740058552871278228167182897293452716491145970928700691 87
UVM_ERROR @ 279442572 ps: (rv_dm_hart_unavail_vseq.sv:24) [uvm_test_top.env.virtual_sequencer.rv_dm_hart_unavail_vseq] Check failed jtag_dmi_ral.dmstatus.anyunavail.get_mirrored_value() == req_unavailable (0 [0x0] vs 1 [0x1])
UVM_INFO @ 279442572 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (rv_dm_jtag_dmi_debug_disabled_vseq.sv:16) [rv_dm_jtag_dmi_debug_disabled_vseq] Check failed rdata == expected_value (* [*] vs * [*])
rv_dm_jtag_dmi_debug_disabled 18983816638691396390428379208098881886012718539312340798053368920843527624499 87
UVM_ERROR @ 232493038 ps: (rv_dm_jtag_dmi_debug_disabled_vseq.sv:16) [uvm_test_top.env.virtual_sequencer.rv_dm_jtag_dmi_debug_disabled_vseq] Check failed rdata == expected_value (2711027780 [0xa1970044] vs 0 [0x0])
UVM_INFO @ 232493038 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Job timed out after * minutes
rv_dm_stress_all 61198372726487671670485234355490538996063813076759885918421399358632777302926 None
Job timed out after 180 minutes
UVM_FATAL (cip_base_vseq.sv:1170) [rv_dm_common_vseq] Check failed (vseq_done)
rv_dm_stress_all_with_rand_reset 85239277740839904183998372237698113339360122264639323799714315638085781673008 106
UVM_FATAL @ 3347544027 ps: (cip_base_vseq.sv:1170) [uvm_test_top.env.virtual_sequencer.rv_dm_common_vseq] Check failed (vseq_done)
UVM_INFO @ 3347544027 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---