Simulation Results: rv_timer

 
02/04/2026 16:07:25 DVSim: v1.17.3 sha: 08f559e json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 97.32 %
  • code
  • 95.85 %
  • assert
  • 96.52 %
  • func
  • 99.58 %
  • block
  • 99.10 %
  • line
  • 99.02 %
  • branch
  • 99.26 %
  • toggle
  • 89.26 %
Validation stages
V1
100.00%
V2
90.91%
V2S
100.00%
V3
33.33%
Testpoint Test Max Runtime Sim Time Pass Total %
random 1 1 100.00
rv_timer_random 1.000s 251.826us 1 1 100.00
csr_hw_reset 1 1 100.00
rv_timer_csr_hw_reset 1.000s 18.651us 1 1 100.00
csr_rw 1 1 100.00
rv_timer_csr_rw 1.000s 40.260us 1 1 100.00
csr_bit_bash 1 1 100.00
rv_timer_csr_bit_bash 2.000s 72.165us 1 1 100.00
csr_aliasing 1 1 100.00
rv_timer_csr_aliasing 1.000s 101.288us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
rv_timer_csr_mem_rw_with_rand_reset 1.000s 29.434us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
rv_timer_csr_rw 1.000s 40.260us 1 1 100.00
rv_timer_csr_aliasing 1.000s 101.288us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
random_reset 0 1 0.00
rv_timer_random_reset 1.000s 397.631us 0 1 0.00
disabled 1 1 100.00
rv_timer_disabled 3.000s 3082.825us 1 1 100.00
cfg_update_on_fly 1 1 100.00
rv_timer_cfg_update_on_fly 1.000s 221.696us 1 1 100.00
no_interrupt_test 1 1 100.00
rv_timer_cfg_update_on_fly 1.000s 221.696us 1 1 100.00
stress 1 1 100.00
rv_timer_stress_all 3.000s 2641.564us 1 1 100.00
alert_test 1 1 100.00
rv_timer_alert_test 1.000s 30.945us 1 1 100.00
intr_test 1 1 100.00
rv_timer_intr_test 1.000s 20.561us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
rv_timer_tl_errors 2.000s 267.109us 1 1 100.00
tl_d_illegal_access 1 1 100.00
rv_timer_tl_errors 2.000s 267.109us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
rv_timer_csr_hw_reset 1.000s 18.651us 1 1 100.00
rv_timer_csr_rw 1.000s 40.260us 1 1 100.00
rv_timer_csr_aliasing 1.000s 101.288us 1 1 100.00
rv_timer_same_csr_outstanding 1.000s 27.463us 1 1 100.00
tl_d_partial_access 4 4 100.00
rv_timer_csr_hw_reset 1.000s 18.651us 1 1 100.00
rv_timer_csr_rw 1.000s 40.260us 1 1 100.00
rv_timer_csr_aliasing 1.000s 101.288us 1 1 100.00
rv_timer_same_csr_outstanding 1.000s 27.463us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
rv_timer_sec_cm 1.000s 139.230us 1 1 100.00
rv_timer_tl_intg_err 1.000s 99.408us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
rv_timer_tl_intg_err 1.000s 99.408us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
min_value 0 1 0.00
rv_timer_min 1.000s 73.582us 0 1 0.00
max_value 0 1 0.00
rv_timer_max 1.000s 87.313us 0 1 0.00
stress_all_with_rand_reset 1 1 100.00
rv_timer_stress_all_with_rand_reset 15.000s 3419.596us 1 1 100.00

Error Messages

   Test seed line log context
UVM_FATAL (rv_timer_base_vseq.sv:165) [intr_state_spinwait] timeout rv_timer_reg_block.intr_state* (addr=*) == *
rv_timer_min 91711149756729136140233644920961065855243233236410213432222500450979433428325 84
UVM_FATAL @ 73582279 ps: (rv_timer_base_vseq.sv:165) [intr_state_spinwait] timeout rv_timer_reg_block.intr_state0 (addr=0xc2d5c704) == 0x1
UVM_INFO @ 73582279 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rv_timer_random_reset 34777162591264185865692262822554623420499519727491590135072636457224223143812 84
UVM_FATAL @ 397630888 ps: (rv_timer_base_vseq.sv:165) [intr_state_spinwait] timeout rv_timer_reg_block.intr_state0 (addr=0x229f5f04) == 0x1
UVM_INFO @ 397630888 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (rv_timer_scoreboard.sv:231) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*])
rv_timer_max 102646204187183332379225312793878202254560315555314858637694757479672737967712 84
UVM_ERROR @ 87313302 ps: (rv_timer_scoreboard.sv:231) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (1 [0x1] vs 0 [0x0])
UVM_INFO @ 87313302 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---