Simulation Results

Simulation Results: spi_device/1r1w

02/04/2026 16:07:25 DVSim: v1.17.3 sha: 08f559e json Branch: master Tool: xcelium [unknown]

Coverage statistics

Total
85.88 %

code
91.64 %

assert
94.64 %

func
71.35 %

block
98.33 %

line
98.77 %

branch
96.96 %

toggle
81.25 %

FSM
89.58 %

Validation stages

V1		100.00%
V2		92.31%
V2S		100.00%
unmapped		100.00%

8/8 passed

100.00 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
smoke				1	1	100.00
	spi_device_flash_and_tpm	106.000s	10110.015us	1	1	100.00
csr_hw_reset				1	1	100.00
	spi_device_csr_hw_reset	2.000s	76.530us	1	1	100.00
csr_rw				1	1	100.00
	spi_device_csr_rw	3.000s	29.627us	1	1	100.00
csr_bit_bash				1	1	100.00
	spi_device_csr_bit_bash	34.000s	9830.022us	1	1	100.00
csr_aliasing				1	1	100.00
	spi_device_csr_aliasing	18.000s	332.345us	1	1	100.00
csr_mem_rw_with_rand_reset				1	1	100.00
	spi_device_csr_mem_rw_with_rand_reset	5.000s	118.558us	1	1	100.00
regwen_csr_and_corresponding_lockable_csr				2	2	100.00
	spi_device_csr_rw	3.000s	29.627us	1	1	100.00
	spi_device_csr_aliasing	18.000s	332.345us	1	1	100.00
mem_walk				1	1	100.00
	spi_device_mem_walk	1.000s	26.876us	1	1	100.00
mem_partial_access				1	1	100.00
	spi_device_mem_partial_access	2.000s	39.047us	1	1	100.00

24/26 passed

92.31 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
csb_read				1	1	100.00
	spi_device_csb_read	2.000s	16.211us	1	1	100.00
mem_parity				0	1	0.00
	spi_device_mem_parity	1.000s	4.434us	0	1	0.00
mem_cfg				0	1	0.00
	spi_device_ram_cfg	1.000s	3.924us	0	1	0.00
tpm_read				1	1	100.00
	spi_device_tpm_rw	5.000s	910.621us	1	1	100.00
tpm_write				1	1	100.00
	spi_device_tpm_rw	5.000s	910.621us	1	1	100.00
tpm_hw_reg				2	2	100.00
	spi_device_tpm_read_hw_reg	4.000s	3700.048us	1	1	100.00
	spi_device_tpm_sts_read	2.000s	20.291us	1	1	100.00
tpm_fully_random_case				1	1	100.00
	spi_device_tpm_all	2.000s	37.352us	1	1	100.00
pass_cmd_filtering				2	2	100.00
	spi_device_pass_cmd_filtering	51.000s	29652.619us	1	1	100.00
	spi_device_flash_all	49.000s	4333.734us	1	1	100.00
pass_addr_translation				2	2	100.00
	spi_device_pass_addr_payload_swap	3.000s	283.991us	1	1	100.00
	spi_device_flash_all	49.000s	4333.734us	1	1	100.00
pass_payload_translation				2	2	100.00
	spi_device_pass_addr_payload_swap	3.000s	283.991us	1	1	100.00
	spi_device_flash_all	49.000s	4333.734us	1	1	100.00
cmd_info_slots				1	1	100.00
	spi_device_flash_all	49.000s	4333.734us	1	1	100.00
cmd_read_status				2	2	100.00
	spi_device_intercept	8.000s	807.206us	1	1	100.00
	spi_device_flash_all	49.000s	4333.734us	1	1	100.00
cmd_read_jedec				2	2	100.00
	spi_device_intercept	8.000s	807.206us	1	1	100.00
	spi_device_flash_all	49.000s	4333.734us	1	1	100.00
cmd_read_sfdp				2	2	100.00
	spi_device_intercept	8.000s	807.206us	1	1	100.00
	spi_device_flash_all	49.000s	4333.734us	1	1	100.00
cmd_fast_read				2	2	100.00
	spi_device_intercept	8.000s	807.206us	1	1	100.00
	spi_device_flash_all	49.000s	4333.734us	1	1	100.00
cmd_read_pipeline				2	2	100.00
	spi_device_intercept	8.000s	807.206us	1	1	100.00
	spi_device_flash_all	49.000s	4333.734us	1	1	100.00
flash_cmd_upload				1	1	100.00
	spi_device_upload	47.000s	6447.419us	1	1	100.00
mailbox_command				1	1	100.00
	spi_device_mailbox	22.000s	2507.807us	1	1	100.00
mailbox_cross_outside_command				1	1	100.00
	spi_device_mailbox	22.000s	2507.807us	1	1	100.00
mailbox_cross_inside_command				1	1	100.00
	spi_device_mailbox	22.000s	2507.807us	1	1	100.00
cmd_read_buffer				2	2	100.00
	spi_device_flash_mode	9.000s	388.926us	1	1	100.00
	spi_device_read_buffer_direct	4.000s	87.831us	1	1	100.00
cmd_dummy_cycle				2	2	100.00
	spi_device_mailbox	22.000s	2507.807us	1	1	100.00
	spi_device_flash_all	49.000s	4333.734us	1	1	100.00
quad_spi				1	1	100.00
	spi_device_flash_all	49.000s	4333.734us	1	1	100.00
dual_spi				1	1	100.00
	spi_device_flash_all	49.000s	4333.734us	1	1	100.00
4b_3b_feature				1	1	100.00
	spi_device_cfg_cmd	3.000s	327.157us	1	1	100.00
write_enable_disable				1	1	100.00
	spi_device_cfg_cmd	3.000s	327.157us	1	1	100.00
TPM_with_flash_or_passthrough_mode				1	1	100.00
	spi_device_flash_and_tpm	106.000s	10110.015us	1	1	100.00
tpm_and_flash_trans_with_min_inactive_time				1	1	100.00
	spi_device_flash_and_tpm_min_idle	93.000s	6944.675us	1	1	100.00
stress_all				1	1	100.00
	spi_device_stress_all	126.000s	7517.061us	1	1	100.00
alert_test				1	1	100.00
	spi_device_alert_test	2.000s	12.196us	1	1	100.00
intr_test				1	1	100.00
	spi_device_intr_test	1.000s	16.936us	1	1	100.00
tl_d_oob_addr_access				1	1	100.00
	spi_device_tl_errors	3.000s	83.477us	1	1	100.00
tl_d_illegal_access				1	1	100.00
	spi_device_tl_errors	3.000s	83.477us	1	1	100.00
tl_d_outstanding_access				4	4	100.00
	spi_device_csr_hw_reset	2.000s	76.530us	1	1	100.00
	spi_device_csr_rw	3.000s	29.627us	1	1	100.00
	spi_device_csr_aliasing	18.000s	332.345us	1	1	100.00
	spi_device_same_csr_outstanding	4.000s	144.450us	1	1	100.00
tl_d_partial_access				4	4	100.00
	spi_device_csr_hw_reset	2.000s	76.530us	1	1	100.00
	spi_device_csr_rw	3.000s	29.627us	1	1	100.00
	spi_device_csr_aliasing	18.000s	332.345us	1	1	100.00
	spi_device_same_csr_outstanding	4.000s	144.450us	1	1	100.00

V2S

2/2 passed

100.00 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
tl_intg_err				2	2	100.00
	spi_device_tl_intg_err	17.000s	299.761us	1	1	100.00
	spi_device_sec_cm	3.000s	184.178us	1	1	100.00
sec_cm_bus_integrity				1	1	100.00
	spi_device_tl_intg_err	17.000s	299.761us	1	1	100.00

unmapped

1/1 passed

100.00 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
Unmapped				1	1	100.00
	spi_device_flash_mode_ignore_cmds	14.000s	1901.547us	1	1	100.00

Error Messages

	Test	seed	line	log context
UVM_ERROR (uvm_hdl_inca.c:743) [UVM/DPI/NOBJ1] name tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.mem[*] cannot be resolved to a hdl object (vlog,vhdl,vlog-slice)
	spi_device_mem_parity	75161704864855089912256847268461603454052692578682777195798606408217367079435	87	UVM_ERROR @ 3713739 ps: (uvm_hdl_inca.c:743) [UVM/DPI/NOBJ1] name tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.mem[40] cannot be resolved to a hdl object (vlog,vhdl,vlog-slice) UVM_ERROR @ 3713739 ps: (spi_device_mem_parity_vseq.sv:44) [uvm_test_top.env.virtual_sequencer.spi_device_mem_parity_vseq] Check failed (uvm_hdl_read(egress_path, mem_data)) ERROR: VHPI NOTFOUND Name tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.mem[936] not found within the scope . UVM_ERROR @ 3713739 ps: (uvm_hdl_inca.c:743) [UVM/DPI/NOBJ2] name tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.mem[936] cannot be resolved to a hdl object (vlog,vhdl,vlog-slice)
UVM_ERROR (spi_device_ram_cfg_vseq.sv:27) [spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (* [] vs [*])
	spi_device_ram_cfg	250492853768939214883366828132397523172904826801870092391332554770088206848	85	UVM_ERROR @ 1386342 ps: (spi_device_ram_cfg_vseq.sv:27) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (0xf6725d [111101100111001001011101] vs 0x0 [0]) UVM_ERROR @ 1436342 ps: (spi_device_ram_cfg_vseq.sv:27) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (0x7e494 [1111110010010010100] vs 0x0 [0]) UVM_ERROR @ 1504342 ps: (spi_device_ram_cfg_vseq.sv:27) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (0xddf510 [110111011111010100010000] vs 0x0 [0]) UVM_ERROR @ 1552342 ps: (spi_device_ram_cfg_vseq.sv:27) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (0x61ca34 [11000011100101000110100] vs 0x0 [0]) UVM_ERROR @ 1642342 ps: (spi_device_ram_cfg_vseq.sv:27) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (0xfb9684 [111110111001011010000100] vs 0x0 [0])