Simulation Results: sram_ctrl/main

 
02/04/2026 16:07:25 DVSim: v1.17.3 sha: 08f559e json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 91.29 %
  • code
  • 83.24 %
  • assert
  • 95.82 %
  • func
  • 94.80 %
  • block
  • 93.98 %
  • line
  • 94.96 %
  • branch
  • 89.08 %
  • toggle
  • 82.24 %
  • FSM
  • 66.67 %
Validation stages
V1
100.00%
V2
90.00%
V2S
80.00%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
sram_ctrl_smoke 34.000s 3201.519us 1 1 100.00
csr_hw_reset 1 1 100.00
sram_ctrl_csr_hw_reset 1.000s 82.856us 1 1 100.00
csr_rw 1 1 100.00
sram_ctrl_csr_rw 1.000s 22.340us 1 1 100.00
csr_bit_bash 1 1 100.00
sram_ctrl_csr_bit_bash 2.000s 167.739us 1 1 100.00
csr_aliasing 1 1 100.00
sram_ctrl_csr_aliasing 1.000s 20.712us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
sram_ctrl_csr_mem_rw_with_rand_reset 2.000s 366.246us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
sram_ctrl_csr_rw 1.000s 22.340us 1 1 100.00
sram_ctrl_csr_aliasing 1.000s 20.712us 1 1 100.00
mem_walk 1 1 100.00
sram_ctrl_mem_walk 204.000s 65748.731us 1 1 100.00
mem_partial_access 1 1 100.00
sram_ctrl_mem_partial_access 92.000s 9847.155us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
multiple_keys 1 1 100.00
sram_ctrl_multiple_keys 107.000s 3960.362us 1 1 100.00
stress_pipeline 1 1 100.00
sram_ctrl_stress_pipeline 183.000s 11892.967us 1 1 100.00
bijection 1 1 100.00
sram_ctrl_bijection 648.000s 184776.465us 1 1 100.00
access_during_key_req 1 1 100.00
sram_ctrl_access_during_key_req 292.000s 36603.233us 1 1 100.00
lc_escalation 1 1 100.00
sram_ctrl_lc_escalation 23.000s 65376.386us 1 1 100.00
executable 1 1 100.00
sram_ctrl_executable 304.000s 14693.135us 1 1 100.00
partial_access 2 2 100.00
sram_ctrl_partial_access 12.000s 2503.535us 1 1 100.00
sram_ctrl_partial_access_b2b 205.000s 28614.470us 1 1 100.00
max_throughput 1 3 33.33
sram_ctrl_max_throughput 3.000s 2737.247us 0 1 0.00
sram_ctrl_throughput_w_partial_write 33.000s 855.458us 1 1 100.00
sram_ctrl_throughput_w_readback 4.000s 3321.203us 0 1 0.00
regwen 1 1 100.00
sram_ctrl_regwen 495.000s 12584.883us 1 1 100.00
ram_cfg 1 1 100.00
sram_ctrl_ram_cfg 6.000s 4181.579us 1 1 100.00
stress_all 1 1 100.00
sram_ctrl_stress_all 4317.000s 114384.492us 1 1 100.00
alert_test 1 1 100.00
sram_ctrl_alert_test 2.000s 21.333us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
sram_ctrl_tl_errors 2.000s 126.769us 1 1 100.00
tl_d_illegal_access 1 1 100.00
sram_ctrl_tl_errors 2.000s 126.769us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
sram_ctrl_csr_hw_reset 1.000s 82.856us 1 1 100.00
sram_ctrl_csr_rw 1.000s 22.340us 1 1 100.00
sram_ctrl_csr_aliasing 1.000s 20.712us 1 1 100.00
sram_ctrl_same_csr_outstanding 1.000s 137.639us 1 1 100.00
tl_d_partial_access 4 4 100.00
sram_ctrl_csr_hw_reset 1.000s 82.856us 1 1 100.00
sram_ctrl_csr_rw 1.000s 22.340us 1 1 100.00
sram_ctrl_csr_aliasing 1.000s 20.712us 1 1 100.00
sram_ctrl_same_csr_outstanding 1.000s 137.639us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
passthru_mem_tl_intg_err 1 1 100.00
sram_ctrl_passthru_mem_tl_intg_err 14.000s 3712.031us 1 1 100.00
tl_intg_err 1 2 50.00
sram_ctrl_sec_cm 1.000s 13.029us 0 1 0.00
sram_ctrl_tl_intg_err 2.000s 1287.963us 1 1 100.00
prim_count_check 0 1 0.00
sram_ctrl_sec_cm 1.000s 13.029us 0 1 0.00
sec_cm_bus_integrity 1 1 100.00
sram_ctrl_tl_intg_err 2.000s 1287.963us 1 1 100.00
sec_cm_ctrl_config_regwen 1 1 100.00
sram_ctrl_regwen 495.000s 12584.883us 1 1 100.00
sec_cm_readback_config_regwen 1 1 100.00
sram_ctrl_regwen 495.000s 12584.883us 1 1 100.00
sec_cm_exec_config_regwen 1 1 100.00
sram_ctrl_csr_rw 1.000s 22.340us 1 1 100.00
sec_cm_exec_config_mubi 1 1 100.00
sram_ctrl_executable 304.000s 14693.135us 1 1 100.00
sec_cm_exec_intersig_mubi 1 1 100.00
sram_ctrl_executable 304.000s 14693.135us 1 1 100.00
sec_cm_lc_hw_debug_en_intersig_mubi 1 1 100.00
sram_ctrl_executable 304.000s 14693.135us 1 1 100.00
sec_cm_lc_escalate_en_intersig_mubi 1 1 100.00
sram_ctrl_lc_escalation 23.000s 65376.386us 1 1 100.00
sec_cm_prim_ram_ctrl_mubi 0 1 0.00
sram_ctrl_mubi_enc_err 6.000s 2673.294us 0 1 0.00
sec_cm_mem_integrity 1 1 100.00
sram_ctrl_passthru_mem_tl_intg_err 14.000s 3712.031us 1 1 100.00
sec_cm_mem_readback 1 1 100.00
sram_ctrl_readback_err 6.000s 692.636us 1 1 100.00
sec_cm_mem_scramble 1 1 100.00
sram_ctrl_smoke 34.000s 3201.519us 1 1 100.00
sec_cm_addr_scramble 1 1 100.00
sram_ctrl_smoke 34.000s 3201.519us 1 1 100.00
sec_cm_instr_bus_lc_gated 1 1 100.00
sram_ctrl_executable 304.000s 14693.135us 1 1 100.00
sec_cm_ram_tl_lc_gate_fsm_sparse 0 1 0.00
sram_ctrl_sec_cm 1.000s 13.029us 0 1 0.00
sec_cm_key_global_esc 1 1 100.00
sram_ctrl_lc_escalation 23.000s 65376.386us 1 1 100.00
sec_cm_key_local_esc 0 1 0.00
sram_ctrl_sec_cm 1.000s 13.029us 0 1 0.00
sec_cm_init_ctr_redun 0 1 0.00
sram_ctrl_sec_cm 1.000s 13.029us 0 1 0.00
sec_cm_scramble_key_sideload 1 1 100.00
sram_ctrl_smoke 34.000s 3201.519us 1 1 100.00
sec_cm_tlul_fifo_ctr_redun 0 1 0.00
sram_ctrl_sec_cm 1.000s 13.029us 0 1 0.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 1 1 100.00
sram_ctrl_stress_all_with_rand_reset 71.000s 22822.461us 1 1 100.00

Error Messages

   Test seed line log context
UVM_FATAL (sram_ctrl_base_vseq.sv:329) [sram_ctrl_throughput_vseq] Check failed (std::randomize(mask) with {$countones(mask ^ {mask[bus_params_pkg::BUS_DBW-*:*], *'b0}) <= *; mask dist {'* :/ * - partial_access_pct, [* : '* - *] :/ partial_access_pct};}) Randomization failed!
sram_ctrl_max_throughput 53823436249853139028666664273129438063353726710408570536307896763573754759348 102
UVM_FATAL @ 2737246660 ps: (sram_ctrl_base_vseq.sv:329) [uvm_test_top.env.virtual_sequencer.sram_ctrl_throughput_vseq] Check failed (std::randomize(mask) with {$countones(mask ^ {mask[bus_params_pkg::BUS_DBW-2:0], 1'b0}) <= 2; mask dist {'1 :/ 100 - partial_access_pct, [0 : '1 - 1] :/ partial_access_pct};}) Randomization failed!
UVM_INFO @ 2737246660 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
sram_ctrl_throughput_w_readback 42143129988638378638037390450065989070821135057857747977975158798669100899380 102
UVM_FATAL @ 3321202859 ps: (sram_ctrl_base_vseq.sv:329) [uvm_test_top.env.virtual_sequencer.sram_ctrl_throughput_vseq] Check failed (std::randomize(mask) with {$countones(mask ^ {mask[bus_params_pkg::BUS_DBW-2:0], 1'b0}) <= 2; mask dist {'1 :/ 100 - partial_access_pct, [0 : '1 - 1] :/ partial_access_pct};}) Randomization failed!
UVM_INFO @ 3321202859 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
xmsim: *E,ASRTST (/nightly/current_run/scratch/master/sram_ctrl_main-sim-xcelium/default/fusesoc-work/src/lowrisc_tlul_adapter_sram_*/rtl/tlul_adapter_sram.sv,636): Assertion rvalidHighReqFifoEmpty has failed
sram_ctrl_mubi_enc_err 16831691232481982620758392130468197760766654588657413804763928122681115360503 89
xmsim: *E,ASRTST (/nightly/current_run/scratch/master/sram_ctrl_main-sim-xcelium/default/fusesoc-work/src/lowrisc_tlul_adapter_sram_0.1/rtl/tlul_adapter_sram.sv,636): (time 2673294306 PS) Assertion tb.dut.u_tlul_adapter_sram_racl.tlul_adapter_sram.rvalidHighReqFifoEmpty has failed
UVM_ERROR @ 2673294306 ps: (tlul_adapter_sram.sv:636) [ASSERT FAILED] rvalidHighReqFifoEmpty
UVM_INFO @ 2673294306 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
xmsim: *E,ASRTST (/nightly/current_run/scratch/master/sram_ctrl_main-sim-xcelium/default/fusesoc-work/src/lowrisc_tlul_common_*/rtl/tlul_assert.sv,290): Assertion respOpcode_A has failed
sram_ctrl_sec_cm 46134790102847258391179048284551549702136780096143864279551134910564691246686 92
xmsim: *E,ASRTST (/nightly/current_run/scratch/master/sram_ctrl_main-sim-xcelium/default/fusesoc-work/src/lowrisc_tlul_common_0.1/rtl/tlul_assert.sv,290): (time 9226844 PS) Assertion tb.dut.tlul_assert_device_ram.gen_device.gen_d2h.respOpcode_A has failed
xmsim: *E,ASRTST (/nightly/current_run/scratch/master/sram_ctrl_main-sim-xcelium/default/fusesoc-work/src/lowrisc_tlul_common_0.1/rtl/tlul_assert.sv,293): (time 9226844 PS) Assertion tb.dut.tlul_assert_device_ram.gen_device.gen_d2h.respMustHaveReq_A has failed
UVM_ERROR @ 13028867 ps: (csr_utils_pkg.sv:458) [csr_utils_pkg::csr_rd_check.isolation_fork.unmblk1] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: sram_ctrl_regs_reg_block.status.init_error reset value: 0x0
UVM_INFO @ 13028867 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---