Simulation Results

Simulation Results: uart

02/04/2026 16:07:25 DVSim: v1.17.3 sha: 08f559e json Branch: master Tool: xcelium [unknown]

Coverage statistics

Total
94.82 %

code
96.65 %

assert
97.12 %

func
90.69 %

block
99.08 %

line
99.52 %

branch
98.34 %

toggle
88.74 %

FSM
100.00 %

Validation stages

V1		100.00%
V2		95.45%
V2S		100.00%
V3		100.00%

6/6 passed

100.00 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
smoke				1	1	100.00
	uart_smoke	14.000s	6046.522us	1	1	100.00
csr_hw_reset				1	1	100.00
	uart_csr_hw_reset	1.000s	24.576us	1	1	100.00
csr_rw				1	1	100.00
	uart_csr_rw	1.000s	15.777us	1	1	100.00
csr_bit_bash				1	1	100.00
	uart_csr_bit_bash	2.000s	181.739us	1	1	100.00
csr_aliasing				1	1	100.00
	uart_csr_aliasing	1.000s	19.250us	1	1	100.00
csr_mem_rw_with_rand_reset				1	1	100.00
	uart_csr_mem_rw_with_rand_reset	1.000s	35.768us	1	1	100.00
regwen_csr_and_corresponding_lockable_csr				2	2	100.00
	uart_csr_rw	1.000s	15.777us	1	1	100.00
	uart_csr_aliasing	1.000s	19.250us	1	1	100.00

21/22 passed

95.45 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
base_random_seq				1	1	100.00
	uart_tx_rx	25.000s	19311.430us	1	1	100.00
parity				2	2	100.00
	uart_smoke	14.000s	6046.522us	1	1	100.00
	uart_tx_rx	25.000s	19311.430us	1	1	100.00
parity_error				2	2	100.00
	uart_intr	17.000s	22992.993us	1	1	100.00
	uart_rx_parity_err	34.000s	23378.360us	1	1	100.00
watermark				2	2	100.00
	uart_tx_rx	25.000s	19311.430us	1	1	100.00
	uart_intr	17.000s	22992.993us	1	1	100.00
fifo_full				1	1	100.00
	uart_fifo_full	46.000s	30845.334us	1	1	100.00
fifo_overflow				1	1	100.00
	uart_fifo_overflow	25.000s	39300.042us	1	1	100.00
fifo_reset				1	1	100.00
	uart_fifo_reset	29.000s	37139.146us	1	1	100.00
rx_frame_err				1	1	100.00
	uart_intr	17.000s	22992.993us	1	1	100.00
rx_break_err				1	1	100.00
	uart_intr	17.000s	22992.993us	1	1	100.00
rx_timeout				1	1	100.00
	uart_intr	17.000s	22992.993us	1	1	100.00
perf				1	1	100.00
	uart_perf	291.000s	9955.182us	1	1	100.00
sys_loopback				1	1	100.00
	uart_loopback	10.000s	4746.124us	1	1	100.00
line_loopback				1	1	100.00
	uart_loopback	10.000s	4746.124us	1	1	100.00
rx_noise_filter				0	1	0.00
	uart_noise_filter	2.000s	799.483us	0	1	0.00
rx_start_bit_filter				1	1	100.00
	uart_rx_start_bit_filter	3.000s	4957.743us	1	1	100.00
tx_overide				1	1	100.00
	uart_tx_ovrd	14.000s	7213.145us	1	1	100.00
rx_oversample				1	1	100.00
	uart_rx_oversample	6.000s	3060.495us	1	1	100.00
long_b2b_transfer				1	1	100.00
	uart_long_xfer_wo_dly	274.000s	175351.820us	1	1	100.00
stress_all				1	1	100.00
	uart_stress_all	123.000s	224181.192us	1	1	100.00
alert_test				1	1	100.00
	uart_alert_test	1.000s	12.775us	1	1	100.00
intr_test				1	1	100.00
	uart_intr_test	1.000s	13.924us	1	1	100.00
tl_d_oob_addr_access				1	1	100.00
	uart_tl_errors	1.000s	152.789us	1	1	100.00
tl_d_illegal_access				1	1	100.00
	uart_tl_errors	1.000s	152.789us	1	1	100.00
tl_d_outstanding_access				4	4	100.00
	uart_csr_hw_reset	1.000s	24.576us	1	1	100.00
	uart_csr_rw	1.000s	15.777us	1	1	100.00
	uart_csr_aliasing	1.000s	19.250us	1	1	100.00
	uart_same_csr_outstanding	1.000s	28.695us	1	1	100.00
tl_d_partial_access				4	4	100.00
	uart_csr_hw_reset	1.000s	24.576us	1	1	100.00
	uart_csr_rw	1.000s	15.777us	1	1	100.00
	uart_csr_aliasing	1.000s	19.250us	1	1	100.00
	uart_same_csr_outstanding	1.000s	28.695us	1	1	100.00

V2S

2/2 passed

100.00 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
tl_intg_err				2	2	100.00
	uart_sec_cm	1.000s	69.613us	1	1	100.00
	uart_tl_intg_err	1.000s	53.734us	1	1	100.00
sec_cm_bus_integrity				1	1	100.00
	uart_tl_intg_err	1.000s	53.734us	1	1	100.00

1/1 passed

100.00 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
stress_all_with_rand_reset				1	1	100.00
	uart_stress_all_with_rand_reset	37.000s	5123.933us	1	1	100.00

Error Messages

	Test	seed	line	log context
UVM_ERROR (uart_scoreboard.sv:379) [scoreboard] Check failed get_field_val(ral.status.rxempty, item.d_data) == rx_empty_exp (* [] vs []) check rx_empty fail: uart_rx_clk_pulses = , rx_q.size = *
	uart_noise_filter	62496290417811552057992026468276936260824677518857265706134687866915676790123	83	UVM_ERROR @ 194765914 ps: (uart_scoreboard.sv:379) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxempty, item.d_data) == rx_empty_exp (0 [0x0] vs 1 [0x1]) check rx_empty fail: uart_rx_clk_pulses = 0, rx_q.size = 0 UVM_ERROR @ 201150523 ps: (uart_scoreboard.sv:379) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxempty, item.d_data) == rx_empty_exp (0 [0x0] vs 1 [0x1]) check rx_empty fail: uart_rx_clk_pulses = 0, rx_q.size = 0 UVM_ERROR @ 201150523 ps: (uart_scoreboard.sv:395) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0 UVM_ERROR @ 206509492 ps: (uart_scoreboard.sv:379) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxempty, item.d_data) == rx_empty_exp (0 [0x0] vs 1 [0x1]) check rx_empty fail: uart_rx_clk_pulses = 0, rx_q.size = 0 UVM_ERROR @ 206509492 ps: (uart_scoreboard.sv:395) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0