Simulation Results: alert_handler

 
06/04/2026 16:07:05 DVSim: v1.17.3 sha: d2f24af json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 79.22 %
  • code
  • 87.84 %
  • assert
  • 97.47 %
  • func
  • 52.35 %
  • block
  • 98.18 %
  • line
  • 99.46 %
  • branch
  • 96.47 %
  • toggle
  • 80.69 %
  • FSM
  • 74.74 %
Validation stages
V1
100.00%
V2
84.21%
V2S
100.00%
V3
0.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
alert_handler_smoke 17.000s 772.402us 1 1 100.00
csr_hw_reset 1 1 100.00
alert_handler_csr_hw_reset 10.000s 50.821us 1 1 100.00
csr_rw 1 1 100.00
alert_handler_csr_rw 17.000s 270.210us 1 1 100.00
csr_bit_bash 1 1 100.00
alert_handler_csr_bit_bash 512.000s 26850.531us 1 1 100.00
csr_aliasing 1 1 100.00
alert_handler_csr_aliasing 301.000s 5235.406us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
alert_handler_csr_mem_rw_with_rand_reset 14.000s 326.282us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
alert_handler_csr_rw 17.000s 270.210us 1 1 100.00
alert_handler_csr_aliasing 301.000s 5235.406us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
esc_accum 1 1 100.00
alert_handler_esc_alert_accum 310.000s 3957.977us 1 1 100.00
esc_timeout 1 1 100.00
alert_handler_esc_intr_timeout 26.000s 312.556us 1 1 100.00
entropy 1 1 100.00
alert_handler_entropy 1413.000s 47018.110us 1 1 100.00
sig_int_fail 1 1 100.00
alert_handler_sig_int_fail 24.000s 811.846us 1 1 100.00
clk_skew 1 1 100.00
alert_handler_smoke 17.000s 772.402us 1 1 100.00
random_alerts 1 1 100.00
alert_handler_random_alerts 95.000s 1369.862us 1 1 100.00
random_classes 1 1 100.00
alert_handler_random_classes 52.000s 752.848us 1 1 100.00
ping_timeout 0 1 0.00
alert_handler_ping_timeout 67.000s 2542.238us 0 1 0.00
lpg 2 2 100.00
alert_handler_lpg 1368.000s 104891.810us 1 1 100.00
alert_handler_lpg_stub_clk 1042.000s 9353.481us 1 1 100.00
stress_all 0 1 0.00
alert_handler_stress_all 133.000s 930.571us 0 1 0.00
alert_handler_entropy_stress_test 1 1 100.00
alert_handler_entropy_stress 44.000s 790.736us 1 1 100.00
alert_handler_alert_accum_saturation 0 1 0.00
alert_handler_alert_accum_saturation 3.000s 0.000us 0 1 0.00
intr_test 1 1 100.00
alert_handler_intr_test 3.000s 16.105us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
alert_handler_tl_errors 30.000s 382.914us 1 1 100.00
tl_d_illegal_access 1 1 100.00
alert_handler_tl_errors 30.000s 382.914us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
alert_handler_csr_hw_reset 10.000s 50.821us 1 1 100.00
alert_handler_csr_rw 17.000s 270.210us 1 1 100.00
alert_handler_csr_aliasing 301.000s 5235.406us 1 1 100.00
alert_handler_same_csr_outstanding 40.000s 388.838us 1 1 100.00
tl_d_partial_access 4 4 100.00
alert_handler_csr_hw_reset 10.000s 50.821us 1 1 100.00
alert_handler_csr_rw 17.000s 270.210us 1 1 100.00
alert_handler_csr_aliasing 301.000s 5235.406us 1 1 100.00
alert_handler_same_csr_outstanding 40.000s 388.838us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
shadow_reg_update_error 1 1 100.00
alert_handler_shadow_reg_errors 301.000s 18841.687us 1 1 100.00
shadow_reg_read_clear_staged_value 1 1 100.00
alert_handler_shadow_reg_errors 301.000s 18841.687us 1 1 100.00
shadow_reg_storage_error 1 1 100.00
alert_handler_shadow_reg_errors 301.000s 18841.687us 1 1 100.00
shadowed_reset_glitch 1 1 100.00
alert_handler_shadow_reg_errors 301.000s 18841.687us 1 1 100.00
shadow_reg_update_error_with_csr_rw 1 1 100.00
alert_handler_shadow_reg_errors_with_csr_rw 332.000s 9152.287us 1 1 100.00
tl_intg_err 2 2 100.00
alert_handler_sec_cm 31.000s 1384.045us 1 1 100.00
alert_handler_tl_intg_err 5.000s 62.882us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
alert_handler_tl_intg_err 5.000s 62.882us 1 1 100.00
sec_cm_config_shadow 1 1 100.00
alert_handler_shadow_reg_errors 301.000s 18841.687us 1 1 100.00
sec_cm_ping_timer_config_regwen 1 1 100.00
alert_handler_smoke 17.000s 772.402us 1 1 100.00
sec_cm_alert_config_regwen 1 1 100.00
alert_handler_smoke 17.000s 772.402us 1 1 100.00
sec_cm_alert_loc_config_regwen 1 1 100.00
alert_handler_smoke 17.000s 772.402us 1 1 100.00
sec_cm_class_config_regwen 1 1 100.00
alert_handler_smoke 17.000s 772.402us 1 1 100.00
sec_cm_alert_intersig_diff 1 1 100.00
alert_handler_sig_int_fail 24.000s 811.846us 1 1 100.00
sec_cm_lpg_intersig_mubi 1 1 100.00
alert_handler_lpg 1368.000s 104891.810us 1 1 100.00
sec_cm_esc_intersig_diff 1 1 100.00
alert_handler_sig_int_fail 24.000s 811.846us 1 1 100.00
sec_cm_alert_rx_intersig_bkgn_chk 1 1 100.00
alert_handler_entropy 1413.000s 47018.110us 1 1 100.00
sec_cm_esc_tx_intersig_bkgn_chk 1 1 100.00
alert_handler_entropy 1413.000s 47018.110us 1 1 100.00
sec_cm_esc_timer_fsm_sparse 1 1 100.00
alert_handler_sec_cm 31.000s 1384.045us 1 1 100.00
sec_cm_ping_timer_fsm_sparse 1 1 100.00
alert_handler_sec_cm 31.000s 1384.045us 1 1 100.00
sec_cm_esc_timer_fsm_local_esc 1 1 100.00
alert_handler_sec_cm 31.000s 1384.045us 1 1 100.00
sec_cm_ping_timer_fsm_local_esc 1 1 100.00
alert_handler_sec_cm 31.000s 1384.045us 1 1 100.00
sec_cm_esc_timer_fsm_global_esc 1 1 100.00
alert_handler_sec_cm 31.000s 1384.045us 1 1 100.00
sec_cm_accu_ctr_redun 1 1 100.00
alert_handler_sec_cm 31.000s 1384.045us 1 1 100.00
sec_cm_esc_timer_ctr_redun 1 1 100.00
alert_handler_sec_cm 31.000s 1384.045us 1 1 100.00
sec_cm_ping_timer_ctr_redun 1 1 100.00
alert_handler_sec_cm 31.000s 1384.045us 1 1 100.00
sec_cm_ping_timer_lfsr_redun 1 1 100.00
alert_handler_sec_cm 31.000s 1384.045us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 0 1 0.00
alert_handler_stress_all_with_rand_reset 288.000s 6343.101us 0 1 0.00

Error Messages

   Test seed line log context
UVM_ERROR (alert_handler_scoreboard.sv:486) [scoreboard] Check failed intr_state_val == item.d_data (* [*] vs * [*]) reg name: intr_state
alert_handler_ping_timeout 74984879793633612089034084399983205638251966536519573041110203093144613258787 93
UVM_ERROR @ 2542238199 ps: (alert_handler_scoreboard.sv:486) [uvm_test_top.env.scoreboard] Check failed intr_state_val == item.d_data (0 [0x0] vs 2 [0x2]) reg name: intr_state
UVM_INFO @ 2542238199 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (alert_handler_scoreboard.sv:491) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) reg name: alert_handler_reg_block.classa_state
alert_handler_stress_all 92653813011496724656609231356590360020960209079807762452095093788835450007052 146
UVM_ERROR @ 930571349 ps: (alert_handler_scoreboard.sv:491) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (1 [0x1] vs 4 [0x4]) reg name: alert_handler_reg_block.classa_state
UVM_INFO @ 930571349 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (uvm_hdl_inca.c:743) [UVM/DPI/NOBJ3] name tb.dut.gen_classes[``i``].u_accu.u_prim_count.cnt_q[*] cannot be resolved to a hdl object (vlog,vhdl,vlog-slice)
alert_handler_alert_accum_saturation 110839842276909710744764100536499981675165509806751389558374152714668922311004 88
UVM_ERROR @ 0 ps: (uvm_hdl_inca.c:743) [UVM/DPI/NOBJ3] name tb.dut.gen_classes[``i``].u_accu.u_prim_count.cnt_q[0] cannot be resolved to a hdl object (vlog,vhdl,vlog-slice)
UVM_INFO @ 0 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_vseq.sv:1237) [alert_handler_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses.
alert_handler_stress_all_with_rand_reset 114367716244880180162545284186691597028264253539855873667027772023325713467701 189
UVM_ERROR @ 6343101097 ps: (cip_base_vseq.sv:1237) [uvm_test_top.env.virtual_sequencer.alert_handler_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 6343101097 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---