| V1 |
|
0.00% |
| V2 |
|
0.00% |
| V2S |
|
0.00% |
| V3 |
|
0.00% |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| smoke | 0 | 1 | 0.00 | |||
| clkmgr_smoke | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| csr_hw_reset | 0 | 1 | 0.00 | |||
| clkmgr_csr_hw_reset | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| csr_rw | 0 | 1 | 0.00 | |||
| clkmgr_csr_rw | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| csr_bit_bash | 0 | 1 | 0.00 | |||
| clkmgr_csr_bit_bash | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| csr_aliasing | 0 | 1 | 0.00 | |||
| clkmgr_csr_aliasing | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| csr_mem_rw_with_rand_reset | 0 | 1 | 0.00 | |||
| clkmgr_csr_mem_rw_with_rand_reset | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| regwen_csr_and_corresponding_lockable_csr | 0 | 2 | 0.00 | |||
| clkmgr_csr_rw | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| clkmgr_csr_aliasing | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| peri_enables | 0 | 1 | 0.00 | |||
| clkmgr_peri | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| trans_enables | 0 | 1 | 0.00 | |||
| clkmgr_trans | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| clk_status | 0 | 1 | 0.00 | |||
| clkmgr_clk_status | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| jitter | 0 | 1 | 0.00 | |||
| clkmgr_smoke | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| frequency | 0 | 1 | 0.00 | |||
| clkmgr_frequency | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| frequency_timeout | 0 | 1 | 0.00 | |||
| clkmgr_frequency_timeout | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| frequency_overflow | 0 | 1 | 0.00 | |||
| clkmgr_frequency | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| stress_all | 0 | 1 | 0.00 | |||
| clkmgr_stress_all | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| alert_test | 0 | 1 | 0.00 | |||
| clkmgr_alert_test | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| tl_d_oob_addr_access | 0 | 1 | 0.00 | |||
| clkmgr_tl_errors | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| tl_d_illegal_access | 0 | 1 | 0.00 | |||
| clkmgr_tl_errors | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| tl_d_outstanding_access | 0 | 4 | 0.00 | |||
| clkmgr_csr_hw_reset | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| clkmgr_csr_rw | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| clkmgr_csr_aliasing | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| clkmgr_same_csr_outstanding | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| tl_d_partial_access | 0 | 4 | 0.00 | |||
| clkmgr_csr_hw_reset | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| clkmgr_csr_rw | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| clkmgr_csr_aliasing | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| clkmgr_same_csr_outstanding | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| tl_intg_err | 0 | 2 | 0.00 | |||
| clkmgr_sec_cm | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| clkmgr_tl_intg_err | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| shadow_reg_update_error | 0 | 1 | 0.00 | |||
| clkmgr_shadow_reg_errors | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| shadow_reg_read_clear_staged_value | 0 | 1 | 0.00 | |||
| clkmgr_shadow_reg_errors | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| shadow_reg_storage_error | 0 | 1 | 0.00 | |||
| clkmgr_shadow_reg_errors | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| shadowed_reset_glitch | 0 | 1 | 0.00 | |||
| clkmgr_shadow_reg_errors | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| shadow_reg_update_error_with_csr_rw | 0 | 1 | 0.00 | |||
| clkmgr_shadow_reg_errors_with_csr_rw | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| sec_cm_bus_integrity | 0 | 1 | 0.00 | |||
| clkmgr_tl_intg_err | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| sec_cm_meas_clk_bkgn_chk | 0 | 1 | 0.00 | |||
| clkmgr_frequency | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| sec_cm_timeout_clk_bkgn_chk | 0 | 1 | 0.00 | |||
| clkmgr_frequency_timeout | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| sec_cm_meas_config_shadow | 0 | 1 | 0.00 | |||
| clkmgr_shadow_reg_errors | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| sec_cm_idle_intersig_mubi | 0 | 1 | 0.00 | |||
| clkmgr_idle_intersig_mubi | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| sec_cm_jitter_config_mubi | 0 | 1 | 0.00 | |||
| clkmgr_csr_rw | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| sec_cm_idle_ctr_redun | 0 | 1 | 0.00 | |||
| clkmgr_sec_cm | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| sec_cm_meas_config_regwen | 0 | 1 | 0.00 | |||
| clkmgr_csr_rw | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| sec_cm_clk_ctrl_config_regwen | 0 | 1 | 0.00 | |||
| clkmgr_csr_rw | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| prim_count_check | 0 | 1 | 0.00 | |||
| clkmgr_sec_cm | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| regwen | 0 | 1 | 0.00 | |||
| clkmgr_regwen | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| stress_all_with_rand_reset | 0 | 1 | 0.00 | |||
| clkmgr_stress_all_with_rand_reset | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| Test | seed | line | log context | |
|---|---|---|---|---|
| xmvlog: *E,ENUMERR (src/lowrisc_darjeeling_dv_clkmgr_env_*/seq_lib/clkmgr_regwen_vseq.sv,*|52): This assignment is a violation of SystemVerilog strong typing rules for enumeration datatypes. | ||||
| default | None | 1005 |
xmvlog: *E,ENUMERR (src/lowrisc_darjeeling_dv_clkmgr_env_0.1/seq_lib/clkmgr_regwen_vseq.sv,21|52): This assignment is a violation of SystemVerilog strong typing rules for enumeration datatypes.
package worklib.clkmgr_env_pkg:sv
errors: 1, warnings: 2
file: src/lowrisc_darjeeling_dv_clkmgr_env_0.1/clkmgr_if.sv
import clkmgr_env_pkg::*;
|
|
| cover_reg_top | None | 1005 |
xmvlog: *E,ENUMERR (src/lowrisc_darjeeling_dv_clkmgr_env_0.1/seq_lib/clkmgr_regwen_vseq.sv,21|52): This assignment is a violation of SystemVerilog strong typing rules for enumeration datatypes.
package worklib.clkmgr_env_pkg:sv
errors: 1, warnings: 2
file: src/lowrisc_darjeeling_dv_clkmgr_env_0.1/clkmgr_if.sv
import clkmgr_env_pkg::*;
|
|
| Job killed most likely because its dependent job failed. | ||||
| clkmgr_smoke | 60142730654921631484334633259733469654747450426803199463620313896096509255423 | None | ||
| clkmgr_frequency | 31001073290362083009277401182401239828574114762349322602146177881334037033128 | None | ||
| clkmgr_frequency_timeout | 11700531201015659287131998732896365299398379312304302885215696708084619432947 | None | ||
| clkmgr_peri | 47111264474637533974293222674795348619550245853081902063856953691311608335353 | None | ||
| clkmgr_trans | 66774789968169737332112708345561238715870500245471836072948227591988389205862 | None | ||
| clkmgr_clk_status | 57189392899259213674079821572139653592684851194064680765875126044222567259253 | None | ||
| clkmgr_idle_intersig_mubi | 81922634065372021611947999231958139347804784429874407110785480238191816766735 | None | ||
| clkmgr_regwen | 34292437937415745284742128952987023470716178228168244208521528131303989132950 | None | ||
| clkmgr_sec_cm | 43504279840453009476784213061576604190317443589002138143428226242847847885050 | None | ||
| clkmgr_stress_all_with_rand_reset | 53303761443506349608733278878896134806130556183575986158176296937316690811769 | None | ||
| clkmgr_stress_all | 9965185734697945870318913963486298150939360331931008025133325848199917077240 | None | ||
| clkmgr_alert_test | 5554145569378886502028803737150525251231815015021971754083890264932561099394 | None | ||
| clkmgr_shadow_reg_errors | 12879069932992422710530016182265027488846798048381314031114344769745859854470 | None | ||
| clkmgr_shadow_reg_errors_with_csr_rw | 72502346203527762572913913305348369878626667951480858907230906022942524722686 | None | ||
| clkmgr_tl_errors | 30265311379911627489835686328795261903807513586004009906796183077000948247641 | None | ||
| clkmgr_tl_intg_err | 66092873872958986616910791764245574063575164258093358824861582806815259648775 | None | ||
| clkmgr_csr_hw_reset | 107135999538551192691960186757580107620281454279944340188501600738919538642164 | None | ||
| clkmgr_csr_rw | 29862444863916520790139920333314120238224810007751344015670300235822958069123 | None | ||
| clkmgr_csr_bit_bash | 84996573715429230849094185141044418834303658378168942081045756692933097805930 | None | ||
| clkmgr_csr_aliasing | 28197579221437110537930223335267880235978167761323092608144995152952474854290 | None | ||
| clkmgr_same_csr_outstanding | 28915230969662324864200098317414764443479280867385756826171505279333161745573 | None | ||
| clkmgr_csr_mem_rw_with_rand_reset | 5519467890612354792770262683727114290160568163682130665809737997022261120197 | None | ||
| clkmgr | None | None | ||
| clkmgr | None | None | ||