Simulation Results: dma

 
06/04/2026 16:07:05 DVSim: v1.17.3 sha: d2f24af json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 83.77 %
  • code
  • 91.85 %
  • assert
  • 95.87 %
  • func
  • 63.60 %
  • block
  • 97.38 %
  • line
  • 96.89 %
  • branch
  • 95.83 %
  • toggle
  • 83.12 %
  • FSM
  • 91.55 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
unmapped
66.67%
Testpoint Test Max Runtime Sim Time Pass Total %
dma_memory_smoke 1 1 100.00
dma_memory_smoke 4.000s 1861.345us 1 1 100.00
dma_handshake_smoke 1 1 100.00
dma_handshake_smoke 7.000s 1278.773us 1 1 100.00
dma_generic_smoke 1 1 100.00
dma_generic_smoke 6.000s 1495.572us 1 1 100.00
csr_hw_reset 1 1 100.00
dma_csr_hw_reset 1.000s 20.560us 1 1 100.00
csr_rw 1 1 100.00
dma_csr_rw 1.000s 95.098us 1 1 100.00
csr_bit_bash 1 1 100.00
dma_csr_bit_bash 11.000s 1260.496us 1 1 100.00
csr_aliasing 1 1 100.00
dma_csr_aliasing 3.000s 278.565us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
dma_csr_mem_rw_with_rand_reset 2.000s 47.236us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
dma_csr_rw 1.000s 95.098us 1 1 100.00
dma_csr_aliasing 3.000s 278.565us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
dma_memory_region_lock 1 1 100.00
dma_memory_region_lock 31.000s 9619.335us 1 1 100.00
dma_memory_tl_error 1 1 100.00
dma_memory_stress 324.000s 29979.293us 1 1 100.00
dma_handshake_tl_error 1 1 100.00
dma_handshake_stress 507.000s 94747.007us 1 1 100.00
dma_handshake_stress 1 1 100.00
dma_handshake_stress 507.000s 94747.007us 1 1 100.00
dma_memory_stress 1 1 100.00
dma_memory_stress 324.000s 29979.293us 1 1 100.00
dma_generic_stress 1 1 100.00
dma_generic_stress 425.000s 204754.489us 1 1 100.00
dma_handshake_mem_buffer_overflow 1 1 100.00
dma_handshake_stress 507.000s 94747.007us 1 1 100.00
dma_abort 1 1 100.00
dma_abort 12.000s 1023.429us 1 1 100.00
dma_stress_all 1 1 100.00
dma_stress_all 55.000s 4536.875us 1 1 100.00
alert_test 1 1 100.00
dma_alert_test 1.000s 15.024us 1 1 100.00
intr_test 1 1 100.00
dma_intr_test 1.000s 37.957us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
dma_tl_errors 3.000s 973.070us 1 1 100.00
tl_d_illegal_access 1 1 100.00
dma_tl_errors 3.000s 973.070us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
dma_csr_hw_reset 1.000s 20.560us 1 1 100.00
dma_csr_rw 1.000s 95.098us 1 1 100.00
dma_csr_aliasing 3.000s 278.565us 1 1 100.00
dma_same_csr_outstanding 2.000s 595.099us 1 1 100.00
tl_d_partial_access 4 4 100.00
dma_csr_hw_reset 1.000s 20.560us 1 1 100.00
dma_csr_rw 1.000s 95.098us 1 1 100.00
dma_csr_aliasing 3.000s 278.565us 1 1 100.00
dma_same_csr_outstanding 2.000s 595.099us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
dma_illegal_addr_range 3 3 100.00
dma_mem_enabled 12.000s 53.379us 1 1 100.00
dma_generic_stress 425.000s 204754.489us 1 1 100.00
dma_handshake_stress 507.000s 94747.007us 1 1 100.00
dma_config_lock 1 1 100.00
dma_config_lock 6.000s 387.918us 1 1 100.00
tl_intg_err 2 2 100.00
dma_sec_cm 1.000s 11.503us 1 1 100.00
dma_tl_intg_err 2.000s 353.221us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
Unmapped 2 3 66.67
dma_short_transfer 95.000s 37883.008us 1 1 100.00
dma_longer_transfer 2.000s 114.021us 1 1 100.00
dma_stress_all_with_rand_reset 5.000s 215.280us 0 1 0.00

Error Messages

   Test seed line log context
UVM_ERROR @ *ps: (cip_base_vseq.sv:1237) [dma_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses.
dma_stress_all_with_rand_reset 83989687381787879684144179089006883193162967598616326035550896559350592531105 106
UVM_ERROR @ 215279945ps: (cip_base_vseq.sv:1237) [uvm_test_top.env.virtual_sequencer.dma_common_vseq] Check failed (!has_outstanding_access()) Waited 10008 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 215279945ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---