Simulation Results: edn/edn0

 
06/04/2026 16:07:05 DVSim: v1.17.3 sha: d2f24af json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 76.19 %
  • code
  • 84.58 %
  • assert
  • 94.91 %
  • func
  • 49.09 %
  • block
  • 94.16 %
  • line
  • 96.83 %
  • branch
  • 87.62 %
  • toggle
  • 70.14 %
  • FSM
  • 83.72 %
Validation stages
V1
100.00%
V2
85.71%
V2S
100.00%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
edn_smoke 1.000s 21.894us 1 1 100.00
csr_hw_reset 1 1 100.00
edn_csr_hw_reset 2.000s 15.783us 1 1 100.00
csr_rw 1 1 100.00
edn_csr_rw 2.000s 25.557us 1 1 100.00
csr_bit_bash 1 1 100.00
edn_csr_bit_bash 4.000s 547.032us 1 1 100.00
csr_aliasing 1 1 100.00
edn_csr_aliasing 2.000s 406.653us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
edn_csr_mem_rw_with_rand_reset 1.000s 26.265us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
edn_csr_rw 2.000s 25.557us 1 1 100.00
edn_csr_aliasing 2.000s 406.653us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
firmware 1 1 100.00
edn_genbits 1.000s 76.058us 1 1 100.00
csrng_commands 1 1 100.00
edn_genbits 1.000s 76.058us 1 1 100.00
genbits 1 1 100.00
edn_genbits 1.000s 76.058us 1 1 100.00
interrupts 0 1 0.00
edn_intr 2.000s 8.374us 0 1 0.00
alerts 1 1 100.00
edn_alert 2.000s 93.292us 1 1 100.00
errs 0 1 0.00
edn_err 1.000s 3.886us 0 1 0.00
disable 2 2 100.00
edn_disable 1.000s 12.729us 1 1 100.00
edn_disable_auto_req_mode 2.000s 40.189us 1 1 100.00
stress_all 1 1 100.00
edn_stress_all 5.000s 514.062us 1 1 100.00
intr_test 1 1 100.00
edn_intr_test 1.000s 34.048us 1 1 100.00
alert_test 1 1 100.00
edn_alert_test 1.000s 14.704us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
edn_tl_errors 3.000s 705.658us 1 1 100.00
tl_d_illegal_access 1 1 100.00
edn_tl_errors 3.000s 705.658us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
edn_csr_hw_reset 2.000s 15.783us 1 1 100.00
edn_csr_rw 2.000s 25.557us 1 1 100.00
edn_csr_aliasing 2.000s 406.653us 1 1 100.00
edn_same_csr_outstanding 2.000s 64.895us 1 1 100.00
tl_d_partial_access 4 4 100.00
edn_csr_hw_reset 2.000s 15.783us 1 1 100.00
edn_csr_rw 2.000s 25.557us 1 1 100.00
edn_csr_aliasing 2.000s 406.653us 1 1 100.00
edn_same_csr_outstanding 2.000s 64.895us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
edn_sec_cm 5.000s 2746.412us 1 1 100.00
edn_tl_intg_err 3.000s 450.385us 1 1 100.00
sec_cm_config_regwen 1 1 100.00
edn_regwen 1.000s 48.309us 1 1 100.00
sec_cm_config_mubi 1 1 100.00
edn_alert 2.000s 93.292us 1 1 100.00
sec_cm_main_sm_fsm_sparse 1 1 100.00
edn_sec_cm 5.000s 2746.412us 1 1 100.00
sec_cm_ack_sm_fsm_sparse 1 1 100.00
edn_sec_cm 5.000s 2746.412us 1 1 100.00
sec_cm_fifo_ctr_redun 1 1 100.00
edn_sec_cm 5.000s 2746.412us 1 1 100.00
sec_cm_ctr_redun 1 1 100.00
edn_sec_cm 5.000s 2746.412us 1 1 100.00
sec_cm_main_sm_ctr_local_esc 2 2 100.00
edn_alert 2.000s 93.292us 1 1 100.00
edn_sec_cm 5.000s 2746.412us 1 1 100.00
sec_cm_cs_rdata_bus_consistency 1 1 100.00
edn_alert 2.000s 93.292us 1 1 100.00
sec_cm_tile_link_bus_integrity 1 1 100.00
edn_tl_intg_err 3.000s 450.385us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 1 1 100.00
edn_stress_all_with_rand_reset 53.000s 27419.734us 1 1 100.00

Error Messages

   Test seed line log context
xmsim: *E,ASRTST (/nightly/current_run/scratch/master/edn_edn0-sim-xcelium/default/fusesoc-work/src/lowrisc_ip_edn_*/rtl/edn_main_sm.sv,44): Assertion u_state_regs_A has failed
edn_intr 113232324368503435072241059841929735467665237489442269422299119841399725221272 126
xmsim: *E,ASRTST (/nightly/current_run/scratch/master/edn_edn0-sim-xcelium/default/fusesoc-work/src/lowrisc_ip_edn_0.1/rtl/edn_main_sm.sv,44): (time 8374094 PS) Assertion tb.dut.u_edn_core.u_edn_main_sm.u_state_regs_A has failed
UVM_ERROR @ 8374094 ps: (edn_main_sm.sv:44) [ASSERT FAILED] u_state_regs_A
UVM_INFO @ 8374094 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
xmsim: *E,ASRTST (/nightly/current_run/scratch/master/edn_edn0-sim-xcelium/default/fusesoc-work/src/lowrisc_prim_count_*/rtl/prim_count.sv,300): Assertion CntErrReported_A has failed (* cycles, starting * PS)
edn_err 110199009285949625079737577235277142908897666614356593866948752584653620775494 147
xmsim: *E,ASRTST (/nightly/current_run/scratch/master/edn_edn0-sim-xcelium/default/fusesoc-work/src/lowrisc_prim_count_0/rtl/prim_count.sv,300): (time 3886295 PS) Assertion tb.dut.u_edn_core.u_prim_count_max_reqs_cntr.CntErrReported_A has failed (2 cycles, starting 3876295 PS)
UVM_ERROR @ 3886295 ps: (prim_count.sv:300) [ASSERT FAILED] CntErrReported_A
UVM_INFO @ 3886295 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---