| V1 |
|
0.00% |
| V2 |
|
0.00% |
| V2S |
|
0.00% |
| V3 |
|
0.00% |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| smoke | 0 | 1 | 0.00 | |||
| edn_smoke | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| csr_hw_reset | 0 | 1 | 0.00 | |||
| edn_csr_hw_reset | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| csr_rw | 0 | 1 | 0.00 | |||
| edn_csr_rw | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| csr_bit_bash | 0 | 1 | 0.00 | |||
| edn_csr_bit_bash | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| csr_aliasing | 0 | 1 | 0.00 | |||
| edn_csr_aliasing | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| csr_mem_rw_with_rand_reset | 0 | 1 | 0.00 | |||
| edn_csr_mem_rw_with_rand_reset | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| regwen_csr_and_corresponding_lockable_csr | 0 | 2 | 0.00 | |||
| edn_csr_rw | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| edn_csr_aliasing | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| firmware | 0 | 1 | 0.00 | |||
| edn_genbits | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| csrng_commands | 0 | 1 | 0.00 | |||
| edn_genbits | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| genbits | 0 | 1 | 0.00 | |||
| edn_genbits | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| interrupts | 0 | 1 | 0.00 | |||
| edn_intr | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| alerts | 0 | 1 | 0.00 | |||
| edn_alert | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| errs | 0 | 1 | 0.00 | |||
| edn_err | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| disable | 0 | 2 | 0.00 | |||
| edn_disable | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| edn_disable_auto_req_mode | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| stress_all | 0 | 1 | 0.00 | |||
| edn_stress_all | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| intr_test | 0 | 1 | 0.00 | |||
| edn_intr_test | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| alert_test | 0 | 1 | 0.00 | |||
| edn_alert_test | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| tl_d_oob_addr_access | 0 | 1 | 0.00 | |||
| edn_tl_errors | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| tl_d_illegal_access | 0 | 1 | 0.00 | |||
| edn_tl_errors | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| tl_d_outstanding_access | 0 | 4 | 0.00 | |||
| edn_csr_hw_reset | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| edn_csr_rw | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| edn_csr_aliasing | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| edn_same_csr_outstanding | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| tl_d_partial_access | 0 | 4 | 0.00 | |||
| edn_csr_hw_reset | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| edn_csr_rw | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| edn_csr_aliasing | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| edn_same_csr_outstanding | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| tl_intg_err | 0 | 2 | 0.00 | |||
| edn_tl_intg_err | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| edn_sec_cm | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| sec_cm_config_regwen | 0 | 1 | 0.00 | |||
| edn_regwen | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| sec_cm_config_mubi | 0 | 1 | 0.00 | |||
| edn_alert | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| sec_cm_main_sm_fsm_sparse | 0 | 1 | 0.00 | |||
| edn_sec_cm | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| sec_cm_ack_sm_fsm_sparse | 0 | 1 | 0.00 | |||
| edn_sec_cm | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| sec_cm_fifo_ctr_redun | 0 | 1 | 0.00 | |||
| edn_sec_cm | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| sec_cm_ctr_redun | 0 | 1 | 0.00 | |||
| edn_sec_cm | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| sec_cm_main_sm_ctr_local_esc | 0 | 2 | 0.00 | |||
| edn_alert | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| edn_sec_cm | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| sec_cm_cs_rdata_bus_consistency | 0 | 1 | 0.00 | |||
| edn_alert | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| sec_cm_tile_link_bus_integrity | 0 | 1 | 0.00 | |||
| edn_tl_intg_err | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| stress_all_with_rand_reset | 0 | 1 | 0.00 | |||
| edn_stress_all_with_rand_reset | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| Test | seed | line | log context | |
|---|---|---|---|---|
| xrun: *E,ELBERR: Error (*E) or soft error (*SE) occurred during elaboration (status *), exiting. | ||||
| default | None | 1077 |
xrun: *E,ELBERR: Error (*E) or soft error (*SE) occurred during elaboration (status 1), exiting.
TOOL: xrun(64) 24.03-s007: Exiting on Apr 06, 2026 at 16:08:42 UTC (total: 00:00:02)
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:36: do_build] Error 1
|
|
| cover_reg_top | None | 1061 |
xrun: *E,ELBERR: Error (*E) or soft error (*SE) occurred during elaboration (status 1), exiting.
TOOL: xrun(64) 24.03-s007: Exiting on Apr 06, 2026 at 16:08:42 UTC (total: 00:00:02)
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:36: do_build] Error 1
|
|
| Job killed most likely because its dependent job failed. | ||||
| edn_tl_errors | 34401098943984067939291132493824641368748984070616225407509654738576860696407 | None | ||
| edn_tl_intg_err | 6152045226171996998289064511584902316092265992812374115752715412417990144394 | None | ||
| edn_intr_test | 60665276035663654222982200222277100356802592651610625994965545516190317051527 | None | ||
| edn_csr_hw_reset | 101778567561451206276899358195623217915400300467042535994812261664546844281265 | None | ||
| edn_csr_rw | 25224014548792640993401333879775135908553961776773928450068706661044548259990 | None | ||
| edn_csr_bit_bash | 34391066366915216295013209724687917526302882838768041404579073331531802002120 | None | ||
| edn_csr_aliasing | 114558052027517701936495451152173318983065827483216427571392346241746643619613 | None | ||
| edn_same_csr_outstanding | 25873052088128349089151664378170742187913714282063765783144100384229955878743 | None | ||
| edn_csr_mem_rw_with_rand_reset | 49642588391711628063118583479809585689869740705365650864410812892160912495294 | None | ||
| edn_smoke | 16094041885587830001705699891335963313203101329567179662154798193369391162992 | None | ||
| edn_regwen | 83690957880644225137778287670505563900653091430894713000841249554530641745773 | None | ||
| edn_genbits | 53394729304751361223414142666748622858465269891409498833218867032161262207282 | None | ||
| edn_stress_all | 110409621138301195285053892507344065694957779343116007727343016472667385347603 | None | ||
| edn_stress_all_with_rand_reset | 7246693193454854943086028634963062685293475564113693488374382630552790714971 | None | ||
| edn_intr | 20548637277157968561295480104394827947551086950104163091051228920631130558963 | None | ||
| edn_alert | 80781243693816733585351179883695868533780035302422593935396189823786006400743 | None | ||
| edn_err | 78639629487182072386679208262416464472046094250744181411627745266739021470905 | None | ||
| edn_disable | 30780521198143399511823961712206496159028770797768362197500706949014926322580 | None | ||
| edn_disable_auto_req_mode | 61985171716137617465216669719389666899449661268606638543378141329004905427980 | None | ||
| edn_sec_cm | 102987782734423744289356405014458380906763921311887397278800016229987707569307 | None | ||
| edn_alert_test | 16429220548118558291178961276998268739731234808413881133018797623692224038591 | None | ||
| edn | None | None | ||
| edn | None | None | ||