| V1 |
|
100.00% |
| V2 |
|
94.12% |
| V2S |
|
100.00% |
| V3 |
|
50.00% |
| unmapped |
|
100.00% |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| smoke | 4 | 4 | 100.00 | |||
| gpio_smoke_en_cdc_prim | 2.000s | 572.387us | 1 | 1 | 100.00 | |
| gpio_smoke_no_pullup_pulldown_en_cdc_prim | 2.000s | 189.043us | 1 | 1 | 100.00 | |
| gpio_smoke | 2.000s | 101.495us | 1 | 1 | 100.00 | |
| gpio_smoke_no_pullup_pulldown | 2.000s | 696.718us | 1 | 1 | 100.00 | |
| csr_hw_reset | 1 | 1 | 100.00 | |||
| gpio_csr_hw_reset | 1.000s | 53.849us | 1 | 1 | 100.00 | |
| csr_rw | 1 | 1 | 100.00 | |||
| gpio_csr_rw | 1.000s | 61.811us | 1 | 1 | 100.00 | |
| csr_bit_bash | 1 | 1 | 100.00 | |||
| gpio_csr_bit_bash | 4.000s | 486.735us | 1 | 1 | 100.00 | |
| csr_aliasing | 1 | 1 | 100.00 | |||
| gpio_csr_aliasing | 1.000s | 47.979us | 1 | 1 | 100.00 | |
| csr_mem_rw_with_rand_reset | 1 | 1 | 100.00 | |||
| gpio_csr_mem_rw_with_rand_reset | 1.000s | 61.381us | 1 | 1 | 100.00 | |
| regwen_csr_and_corresponding_lockable_csr | 2 | 2 | 100.00 | |||
| gpio_csr_rw | 1.000s | 61.811us | 1 | 1 | 100.00 | |
| gpio_csr_aliasing | 1.000s | 47.979us | 1 | 1 | 100.00 | |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| direct_and_masked_out | 2 | 2 | 100.00 | |||
| gpio_random_dout_din | 2.000s | 92.041us | 1 | 1 | 100.00 | |
| gpio_random_dout_din_no_pullup_pulldown | 1.000s | 25.155us | 1 | 1 | 100.00 | |
| out_in_regs_read_write | 1 | 1 | 100.00 | |||
| gpio_dout_din_regs_random_rw | 2.000s | 425.432us | 1 | 1 | 100.00 | |
| gpio_interrupt_programming | 1 | 1 | 100.00 | |||
| gpio_intr_rand_pgm | 2.000s | 320.630us | 1 | 1 | 100.00 | |
| random_interrupt_trigger | 1 | 1 | 100.00 | |||
| gpio_rand_intr_trigger | 2.000s | 96.131us | 1 | 1 | 100.00 | |
| interrupt_and_noise_filter | 1 | 1 | 100.00 | |||
| gpio_intr_with_filter_rand_intr_event | 2.000s | 66.266us | 1 | 1 | 100.00 | |
| noise_filter_stress | 1 | 1 | 100.00 | |||
| gpio_filter_stress | 11.000s | 400.016us | 1 | 1 | 100.00 | |
| regs_long_reads_and_writes | 1 | 1 | 100.00 | |||
| gpio_random_long_reg_writes_reg_reads | 6.000s | 1835.943us | 1 | 1 | 100.00 | |
| full_random | 1 | 1 | 100.00 | |||
| gpio_full_random | 2.000s | 103.349us | 1 | 1 | 100.00 | |
| stress_all | 0 | 1 | 0.00 | |||
| gpio_stress_all | 27.000s | 6051.071us | 0 | 1 | 0.00 | |
| alert_test | 1 | 1 | 100.00 | |||
| gpio_alert_test | 1.000s | 11.905us | 1 | 1 | 100.00 | |
| intr_test | 1 | 1 | 100.00 | |||
| gpio_intr_test | 1.000s | 55.381us | 1 | 1 | 100.00 | |
| tl_d_oob_addr_access | 1 | 1 | 100.00 | |||
| gpio_tl_errors | 2.000s | 746.015us | 1 | 1 | 100.00 | |
| tl_d_illegal_access | 1 | 1 | 100.00 | |||
| gpio_tl_errors | 2.000s | 746.015us | 1 | 1 | 100.00 | |
| tl_d_outstanding_access | 4 | 4 | 100.00 | |||
| gpio_csr_rw | 1.000s | 61.811us | 1 | 1 | 100.00 | |
| gpio_same_csr_outstanding | 2.000s | 30.127us | 1 | 1 | 100.00 | |
| gpio_csr_aliasing | 1.000s | 47.979us | 1 | 1 | 100.00 | |
| gpio_csr_hw_reset | 1.000s | 53.849us | 1 | 1 | 100.00 | |
| tl_d_partial_access | 4 | 4 | 100.00 | |||
| gpio_csr_rw | 1.000s | 61.811us | 1 | 1 | 100.00 | |
| gpio_same_csr_outstanding | 2.000s | 30.127us | 1 | 1 | 100.00 | |
| gpio_csr_aliasing | 1.000s | 47.979us | 1 | 1 | 100.00 | |
| gpio_csr_hw_reset | 1.000s | 53.849us | 1 | 1 | 100.00 | |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| tl_intg_err | 2 | 2 | 100.00 | |||
| gpio_tl_intg_err | 3.000s | 602.329us | 1 | 1 | 100.00 | |
| gpio_sec_cm | 1.000s | 1098.795us | 1 | 1 | 100.00 | |
| sec_cm_bus_integrity | 1 | 1 | 100.00 | |||
| gpio_tl_intg_err | 3.000s | 602.329us | 1 | 1 | 100.00 | |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| straps_data | 1 | 1 | 100.00 | |||
| gpio_rand_straps | 2.000s | 74.940us | 1 | 1 | 100.00 | |
| stress_all_with_rand_reset | 0 | 1 | 0.00 | |||
| gpio_stress_all_with_rand_reset | 1.000s | 1.643us | 0 | 1 | 0.00 | |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| Unmapped | 1 | 1 | 100.00 | |||
| gpio_inp_prd_cnt | 1.000s | 21.894us | 1 | 1 | 100.00 | |
| Test | seed | line | log context | |
|---|---|---|---|---|
| UVM_ERROR (gpio_scoreboard.sv:248) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) | ||||
| gpio_stress_all | 99114493850151989711050604650714448059549612018368608936814047241425774435907 | 301 |
UVM_ERROR @ 6051070898 ps: (gpio_scoreboard.sv:248) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (3423788788 [0xcc12def4] vs 2286442486 [0x884857f6])
UVM_INFO @ 6051070898 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| UVM_FATAL sequencer [SEQDEFPRI] Sequence m_tl_host_base_seq has illegal priority: -* | ||||
| gpio_stress_all_with_rand_reset | 68778712090002713158290978748789952713989015491784925721197624471786444497210 | 87 |
UVM_FATAL @ 1642923 ps: uvm_test_top.env.m_tl_agent_gpio_reg_block.sequencer [SEQDEFPRI] Sequence m_tl_host_base_seq has illegal priority: -1
UVM_INFO @ 1642923 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|