Simulation Results: hmac

 
06/04/2026 16:07:05 DVSim: v1.17.3 sha: d2f24af json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 73.60 %
  • code
  • 95.95 %
  • assert
  • 95.86 %
  • func
  • 28.99 %
  • block
  • 97.46 %
  • line
  • 98.39 %
  • branch
  • 93.64 %
  • toggle
  • 96.96 %
  • FSM
  • 94.83 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
V3
100.00%
unmapped
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
hmac_smoke 11.000s 786.705us 1 1 100.00
csr_hw_reset 1 1 100.00
hmac_csr_hw_reset 2.000s 135.443us 1 1 100.00
csr_rw 1 1 100.00
hmac_csr_rw 1.000s 58.082us 1 1 100.00
csr_bit_bash 1 1 100.00
hmac_csr_bit_bash 5.000s 112.651us 1 1 100.00
csr_aliasing 1 1 100.00
hmac_csr_aliasing 5.000s 523.214us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
hmac_csr_mem_rw_with_rand_reset 2.000s 84.537us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
hmac_csr_rw 1.000s 58.082us 1 1 100.00
hmac_csr_aliasing 5.000s 523.214us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
long_msg 1 1 100.00
hmac_long_msg 1.000s 55.578us 1 1 100.00
back_pressure 1 1 100.00
hmac_back_pressure 75.000s 15551.608us 1 1 100.00
test_vectors 6 6 100.00
hmac_test_sha256_vectors 10.000s 395.047us 1 1 100.00
hmac_test_sha384_vectors 355.000s 38825.232us 1 1 100.00
hmac_test_sha512_vectors 25.000s 1231.171us 1 1 100.00
hmac_test_hmac256_vectors 9.000s 198.759us 1 1 100.00
hmac_test_hmac384_vectors 12.000s 321.839us 1 1 100.00
hmac_test_hmac512_vectors 18.000s 1736.855us 1 1 100.00
burst_wr 1 1 100.00
hmac_burst_wr 29.000s 10171.177us 1 1 100.00
datapath_stress 1 1 100.00
hmac_datapath_stress 99.000s 9954.357us 1 1 100.00
error 1 1 100.00
hmac_error 59.000s 1457.201us 1 1 100.00
wipe_secret 1 1 100.00
hmac_wipe_secret 24.000s 773.993us 1 1 100.00
save_and_restore 6 6 100.00
hmac_smoke 11.000s 786.705us 1 1 100.00
hmac_long_msg 1.000s 55.578us 1 1 100.00
hmac_back_pressure 75.000s 15551.608us 1 1 100.00
hmac_datapath_stress 99.000s 9954.357us 1 1 100.00
hmac_burst_wr 29.000s 10171.177us 1 1 100.00
hmac_stress_all 424.000s 10691.716us 1 1 100.00
fifo_empty_status_interrupt 11 11 100.00
hmac_smoke 11.000s 786.705us 1 1 100.00
hmac_long_msg 1.000s 55.578us 1 1 100.00
hmac_back_pressure 75.000s 15551.608us 1 1 100.00
hmac_datapath_stress 99.000s 9954.357us 1 1 100.00
hmac_wipe_secret 24.000s 773.993us 1 1 100.00
hmac_test_sha256_vectors 10.000s 395.047us 1 1 100.00
hmac_test_sha384_vectors 355.000s 38825.232us 1 1 100.00
hmac_test_sha512_vectors 25.000s 1231.171us 1 1 100.00
hmac_test_hmac256_vectors 9.000s 198.759us 1 1 100.00
hmac_test_hmac384_vectors 12.000s 321.839us 1 1 100.00
hmac_test_hmac512_vectors 18.000s 1736.855us 1 1 100.00
wide_digest_configurable_key_length 14 14 100.00
hmac_smoke 11.000s 786.705us 1 1 100.00
hmac_long_msg 1.000s 55.578us 1 1 100.00
hmac_back_pressure 75.000s 15551.608us 1 1 100.00
hmac_datapath_stress 99.000s 9954.357us 1 1 100.00
hmac_burst_wr 29.000s 10171.177us 1 1 100.00
hmac_error 59.000s 1457.201us 1 1 100.00
hmac_wipe_secret 24.000s 773.993us 1 1 100.00
hmac_test_sha256_vectors 10.000s 395.047us 1 1 100.00
hmac_test_sha384_vectors 355.000s 38825.232us 1 1 100.00
hmac_test_sha512_vectors 25.000s 1231.171us 1 1 100.00
hmac_test_hmac256_vectors 9.000s 198.759us 1 1 100.00
hmac_test_hmac384_vectors 12.000s 321.839us 1 1 100.00
hmac_test_hmac512_vectors 18.000s 1736.855us 1 1 100.00
hmac_stress_all 424.000s 10691.716us 1 1 100.00
stress_all 1 1 100.00
hmac_stress_all 424.000s 10691.716us 1 1 100.00
alert_test 1 1 100.00
hmac_alert_test 1.000s 14.453us 1 1 100.00
intr_test 1 1 100.00
hmac_intr_test 1.000s 46.317us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
hmac_tl_errors 2.000s 63.438us 1 1 100.00
tl_d_illegal_access 1 1 100.00
hmac_tl_errors 2.000s 63.438us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
hmac_csr_hw_reset 2.000s 135.443us 1 1 100.00
hmac_csr_rw 1.000s 58.082us 1 1 100.00
hmac_csr_aliasing 5.000s 523.214us 1 1 100.00
hmac_same_csr_outstanding 2.000s 50.886us 1 1 100.00
tl_d_partial_access 4 4 100.00
hmac_csr_hw_reset 2.000s 135.443us 1 1 100.00
hmac_csr_rw 1.000s 58.082us 1 1 100.00
hmac_csr_aliasing 5.000s 523.214us 1 1 100.00
hmac_same_csr_outstanding 2.000s 50.886us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
hmac_sec_cm 2.000s 226.112us 1 1 100.00
hmac_tl_intg_err 3.000s 177.724us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
hmac_tl_intg_err 3.000s 177.724us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
write_config_and_secret_key_during_msg_wr 1 1 100.00
hmac_smoke 11.000s 786.705us 1 1 100.00
stress_reset 1 1 100.00
hmac_stress_reset 4.000s 148.493us 1 1 100.00
stress_all_with_rand_reset 1 1 100.00
hmac_stress_all_with_rand_reset 50.000s 3588.826us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
Unmapped 1 1 100.00
hmac_directed 2.000s 30.810us 1 1 100.00