Simulation Results: i2c

 
06/04/2026 16:07:05 DVSim: v1.17.3 sha: d2f24af json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 88.14 %
  • code
  • 89.00 %
  • assert
  • 96.19 %
  • func
  • 79.24 %
  • block
  • 95.82 %
  • line
  • 95.20 %
  • branch
  • 92.48 %
  • toggle
  • 86.31 %
  • FSM
  • 82.01 %
Validation stages
V1
100.00%
V2
73.17%
V2S
100.00%
V3
0.00%
Testpoint Test Max Runtime Sim Time Pass Total %
host_smoke 1 1 100.00
i2c_host_smoke 17.000s 3576.521us 1 1 100.00
target_smoke 1 1 100.00
i2c_target_smoke 18.000s 1765.005us 1 1 100.00
csr_hw_reset 1 1 100.00
i2c_csr_hw_reset 1.000s 43.195us 1 1 100.00
csr_rw 1 1 100.00
i2c_csr_rw 1.000s 78.399us 1 1 100.00
csr_bit_bash 1 1 100.00
i2c_csr_bit_bash 4.000s 1458.186us 1 1 100.00
csr_aliasing 1 1 100.00
i2c_csr_aliasing 2.000s 55.135us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
i2c_csr_mem_rw_with_rand_reset 1.000s 25.811us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
i2c_csr_rw 1.000s 78.399us 1 1 100.00
i2c_csr_aliasing 2.000s 55.135us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
host_error_intr 0 1 0.00
i2c_host_error_intr 1.000s 34.274us 0 1 0.00
host_stress_all 0 1 0.00
i2c_host_stress_all 1.000s 207.823us 0 1 0.00
host_maxperf 1 1 100.00
i2c_host_perf 4.000s 645.227us 1 1 100.00
host_override 1 1 100.00
i2c_host_override 1.000s 28.287us 1 1 100.00
host_fifo_watermark 0 1 0.00
i2c_host_fifo_watermark 0.000s 0.000us 0 1 0.00
host_fifo_overflow 1 1 100.00
i2c_host_fifo_overflow 2308.000s 2300.665us 1 1 100.00
host_fifo_reset 3 3 100.00
i2c_host_fifo_reset_fmt 2.000s 449.520us 1 1 100.00
i2c_host_fifo_fmt_empty 7.000s 1168.598us 1 1 100.00
i2c_host_fifo_reset_rx 2.000s 133.626us 1 1 100.00
host_fifo_full 1 1 100.00
i2c_host_fifo_full 39.000s 24245.664us 1 1 100.00
host_timeout 1 1 100.00
i2c_host_stretch_timeout 14.000s 4868.229us 1 1 100.00
i2c_host_mode_toggle 0 1 0.00
i2c_host_mode_toggle 3.000s 301.218us 0 1 0.00
target_glitch 0 1 0.00
i2c_target_glitch 3.000s 2073.838us 0 1 0.00
target_stress_all 0 1 0.00
i2c_target_stress_all 0.000s 0.000us 0 1 0.00
target_maxperf 1 1 100.00
i2c_target_perf 4.000s 2306.899us 1 1 100.00
target_fifo_empty 2 2 100.00
i2c_target_stress_rd 35.000s 4745.349us 1 1 100.00
i2c_target_intr_smoke 5.000s 934.301us 1 1 100.00
target_fifo_reset 2 2 100.00
i2c_target_fifo_reset_acq 2.000s 247.425us 1 1 100.00
i2c_target_fifo_reset_tx 1.000s 202.756us 1 1 100.00
target_fifo_full 1 3 33.33
i2c_target_stress_wr 0.000s 0.000us 0 1 0.00
i2c_target_stress_rd 35.000s 4745.349us 1 1 100.00
i2c_target_intr_stress_wr 0.000s 0.000us 0 1 0.00
target_timeout 1 1 100.00
i2c_target_timeout 7.000s 5277.013us 1 1 100.00
target_clock_stretch 1 1 100.00
i2c_target_stretch 1825.000s 2358.413us 1 1 100.00
bad_address 1 1 100.00
i2c_target_bad_addr 6.000s 6881.075us 1 1 100.00
target_mode_glitch 0 1 0.00
i2c_target_hrst 13.000s 10039.950us 0 1 0.00
target_fifo_watermark 2 2 100.00
i2c_target_fifo_watermarks_acq 4.000s 2368.294us 1 1 100.00
i2c_target_fifo_watermarks_tx 3.000s 445.442us 1 1 100.00
host_mode_config_perf 1 2 50.00
i2c_host_perf 4.000s 645.227us 1 1 100.00
i2c_host_perf_precise 0.000s 0.000us 0 1 0.00
host_mode_clock_stretching 1 1 100.00
i2c_host_stretch_timeout 14.000s 4868.229us 1 1 100.00
target_mode_tx_stretch_ctrl 0 1 0.00
i2c_target_tx_stretch_ctrl 1.000s 2.411us 0 1 0.00
target_mode_nack_generation 3 3 100.00
i2c_target_nack_acqfull 3.000s 2024.319us 1 1 100.00
i2c_target_nack_acqfull_addr 3.000s 3874.281us 1 1 100.00
i2c_target_nack_txstretch 2.000s 121.557us 1 1 100.00
host_mode_halt_on_nak 1 1 100.00
i2c_host_may_nack 4.000s 1262.189us 1 1 100.00
target_mode_smbus_maxlen 1 1 100.00
i2c_target_smbus_maxlen 4.000s 3343.884us 1 1 100.00
alert_test 1 1 100.00
i2c_alert_test 1.000s 32.924us 1 1 100.00
intr_test 1 1 100.00
i2c_intr_test 1.000s 45.026us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
i2c_tl_errors 1.000s 51.019us 1 1 100.00
tl_d_illegal_access 1 1 100.00
i2c_tl_errors 1.000s 51.019us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
i2c_csr_hw_reset 1.000s 43.195us 1 1 100.00
i2c_csr_rw 1.000s 78.399us 1 1 100.00
i2c_csr_aliasing 2.000s 55.135us 1 1 100.00
i2c_same_csr_outstanding 2.000s 145.020us 1 1 100.00
tl_d_partial_access 4 4 100.00
i2c_csr_hw_reset 1.000s 43.195us 1 1 100.00
i2c_csr_rw 1.000s 78.399us 1 1 100.00
i2c_csr_aliasing 2.000s 55.135us 1 1 100.00
i2c_same_csr_outstanding 2.000s 145.020us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
i2c_sec_cm 1.000s 42.455us 1 1 100.00
i2c_tl_intg_err 2.000s 378.403us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
i2c_tl_intg_err 2.000s 378.403us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
host_stress_all_with_rand_reset 0 1 0.00
i2c_host_stress_all_with_rand_reset 11.000s 305.479us 0 1 0.00
target_error_intr 0 1 0.00
i2c_target_unexp_stop 2.000s 58.004us 0 1 0.00
target_stress_all_with_rand_reset 0 1 0.00
i2c_target_stress_all_with_rand_reset 8.000s 687.895us 0 1 0.00

Error Messages

   Test seed line log context
Job timed out after * minutes
i2c_host_fifo_watermark 49397752782038763961619884210448284350867921100648752736894633763471231266908 None
Job timed out after 60 minutes
i2c_host_perf_precise 15950496915922061365558593008820460312946075340857574841931163517798230755725 None
Job timed out after 60 minutes
i2c_target_stress_wr 49382638963198636490694321085072772614515131915555788205505320193948481724937 None
Job timed out after 60 minutes
i2c_target_intr_stress_wr 19789265785476878928525244500030055142853754956159271651807314356799942937584 None
Job timed out after 60 minutes
i2c_target_stress_all 48065832881311336062100475353647089820887513584039711043419678214639055935754 None
Job timed out after 60 minutes
UVM_ERROR sequencer [sequencer] Get_next_item called twice without item_done or get in between
i2c_host_error_intr 26791062855803595239920469758625253645163766466127863782456534853893214528922 108
UVM_ERROR @ 34274374 ps: uvm_test_top.env.m_i2c_agent.sequencer [uvm_test_top.env.m_i2c_agent.sequencer] Get_next_item called twice without item_done or get in between
UVM_INFO @ 34274374 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
i2c_host_stress_all 5729173575910034148801134719551897148659757868709001007534720102137025245405 128
UVM_ERROR @ 207823070 ps: uvm_test_top.env.m_i2c_agent.sequencer [uvm_test_top.env.m_i2c_agent.sequencer] Get_next_item called twice without item_done or get in between
UVM_INFO @ 207823070 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR sequencer [sequencer] get_next_item/try_next_item called twice without item_done or get in between
i2c_target_glitch 41496774351982422288017110615230968481814760367058428619800049630205959773778 93
UVM_ERROR @ 2073838414 ps: uvm_test_top.env.m_i2c_agent.sequencer [uvm_test_top.env.m_i2c_agent.sequencer] get_next_item/try_next_item called twice without item_done or get in between
UVM_INFO @ 2073838414 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (i2c_scoreboard.sv:682) [scoreboard] Check failed obs.data_q[i] == exp.data_q[i] (* [*] vs * [*])
i2c_target_unexp_stop 12099659353918353303746036044520317751595810316252482790145879229793277833247 87
UVM_ERROR @ 58004026 ps: (i2c_scoreboard.sv:682) [uvm_test_top.env.scoreboard] Check failed obs.data_q[i] == exp.data_q[i] (255 [0xff] vs 193 [0xc1])
UVM_INFO @ 58004026 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (i2c_target_hrst_vseq.sv:107) [target_hrst_vseq] wait timeout occurred!
i2c_target_hrst 107966059004294753653077907170986371246252590789641660112778267351039936451683 88
UVM_FATAL @ 10039949923 ps: (i2c_target_hrst_vseq.sv:107) [target_hrst_vseq] wait timeout occurred!
UVM_INFO @ 10039949923 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_vseq.sv:1237) [i2c_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses.
i2c_host_stress_all_with_rand_reset 63208231809527250223438022843238995676573146356806084491323221124234723057121 105
UVM_ERROR @ 305479062 ps: (cip_base_vseq.sv:1237) [uvm_test_top.env.virtual_sequencer.i2c_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 305479062 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
i2c_target_stress_all_with_rand_reset 2757782576467525398295254260209405588524467690946820731531415053907195584508 95
UVM_ERROR @ 687895262 ps: (cip_base_vseq.sv:1237) [uvm_test_top.env.virtual_sequencer.i2c_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 687895262 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (i2c_scoreboard.sv:716) [scoreboard] controller_mode_rd_obs_fifo item uncompared:
i2c_host_mode_toggle 33775507992505752393652773380575387575438505485092211124298622259814311186724 94
UVM_ERROR @ 301218257 ps: (i2c_scoreboard.sv:716) [uvm_test_top.env.scoreboard] controller_mode_rd_obs_fifo item uncompared:
----------------------------------------------------
Name Type Size Value
----------------------------------------------------
mon_dut_item i2c_item - @16497
UVM_FATAL (i2c_base_vseq.sv:882) [i2c_target_tx_stretch_ctrl_vseq] Check failed (std::randomize(transfer_lengths) with {transfer_lengths.size() == num_transfers; transfer_lengths.sum() == num_data_total; foreach (transfer_lengths[i]) { transfer_lengths[i] inside {[cfg.min_xfer_len : num_data_total]}; } transfer_lengths[*] > *; transfer_lengths[num_transfers - *] > *;}) Randomization failed!
i2c_target_tx_stretch_ctrl 38303027442396101442920158442453755489723944908336503398602396551375026353950 110
UVM_FATAL @ 2411344 ps: (i2c_base_vseq.sv:882) [uvm_test_top.env.virtual_sequencer.i2c_target_tx_stretch_ctrl_vseq] Check failed (std::randomize(transfer_lengths) with {transfer_lengths.size() == num_transfers; transfer_lengths.sum() == num_data_total; foreach (transfer_lengths[i]) { transfer_lengths[i] inside {[cfg.min_xfer_len : num_data_total]}; } transfer_lengths[0] > 0; transfer_lengths[num_transfers - 1] > 0;}) Randomization failed!
UVM_INFO @ 2411344 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---