Simulation Results: lc_ctrl/volatile_unlock_disabled

 
06/04/2026 16:07:05 DVSim: v1.17.3 sha: d2f24af json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 92.00 %
  • code
  • 93.40 %
  • assert
  • 95.97 %
  • func
  • 86.62 %
  • block
  • 96.66 %
  • line
  • 97.29 %
  • branch
  • 91.49 %
  • toggle
  • 89.59 %
  • FSM
  • 95.24 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
lc_ctrl_smoke 4.000s 173.096us 1 1 100.00
csr_hw_reset 1 1 100.00
lc_ctrl_csr_hw_reset 2.000s 36.650us 1 1 100.00
csr_rw 1 1 100.00
lc_ctrl_csr_rw 1.000s 28.415us 1 1 100.00
csr_bit_bash 1 1 100.00
lc_ctrl_csr_bit_bash 2.000s 79.674us 1 1 100.00
csr_aliasing 1 1 100.00
lc_ctrl_csr_aliasing 2.000s 33.817us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
lc_ctrl_csr_mem_rw_with_rand_reset 2.000s 33.988us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
lc_ctrl_csr_rw 1.000s 28.415us 1 1 100.00
lc_ctrl_csr_aliasing 2.000s 33.817us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
state_post_trans 1 1 100.00
lc_ctrl_state_post_trans 3.000s 245.016us 1 1 100.00
regwen_during_op 1 1 100.00
lc_ctrl_regwen_during_op 5.000s 301.929us 1 1 100.00
rand_wr_claim_transition_if 1 1 100.00
lc_ctrl_claim_transition_if 1.000s 14.079us 1 1 100.00
lc_prog_failure 1 1 100.00
lc_ctrl_prog_failure 2.000s 522.647us 1 1 100.00
lc_state_failure 1 1 100.00
lc_ctrl_state_failure 4.000s 422.477us 1 1 100.00
lc_errors 1 1 100.00
lc_ctrl_errors 7.000s 400.766us 1 1 100.00
security_escalation 7 7 100.00
lc_ctrl_state_failure 4.000s 422.477us 1 1 100.00
lc_ctrl_prog_failure 2.000s 522.647us 1 1 100.00
lc_ctrl_errors 7.000s 400.766us 1 1 100.00
lc_ctrl_security_escalation 6.000s 348.355us 1 1 100.00
lc_ctrl_jtag_state_failure 11.000s 1045.881us 1 1 100.00
lc_ctrl_jtag_prog_failure 3.000s 310.956us 1 1 100.00
lc_ctrl_jtag_errors 43.000s 12127.506us 1 1 100.00
jtag_access 13 13 100.00
lc_ctrl_jtag_csr_hw_reset 2.000s 65.361us 1 1 100.00
lc_ctrl_jtag_csr_rw 3.000s 328.490us 1 1 100.00
lc_ctrl_jtag_csr_bit_bash 14.000s 1349.091us 1 1 100.00
lc_ctrl_jtag_csr_aliasing 6.000s 3699.212us 1 1 100.00
lc_ctrl_jtag_same_csr_outstanding 2.000s 16.376us 1 1 100.00
lc_ctrl_jtag_csr_mem_rw_with_rand_reset 4.000s 327.260us 1 1 100.00
lc_ctrl_jtag_alert_test 2.000s 248.220us 1 1 100.00
lc_ctrl_jtag_smoke 6.000s 710.982us 1 1 100.00
lc_ctrl_jtag_state_post_trans 5.000s 539.416us 1 1 100.00
lc_ctrl_jtag_prog_failure 3.000s 310.956us 1 1 100.00
lc_ctrl_jtag_errors 43.000s 12127.506us 1 1 100.00
lc_ctrl_jtag_access 6.000s 627.543us 1 1 100.00
lc_ctrl_jtag_regwen_during_op 18.000s 2425.486us 1 1 100.00
jtag_priority 1 1 100.00
lc_ctrl_jtag_priority 6.000s 1456.741us 1 1 100.00
lc_ctrl_volatile_unlock 1 1 100.00
lc_ctrl_volatile_unlock_smoke 2.000s 46.464us 1 1 100.00
stress_all 1 1 100.00
lc_ctrl_stress_all 70.000s 4136.762us 1 1 100.00
alert_test 1 1 100.00
lc_ctrl_alert_test 2.000s 32.279us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
lc_ctrl_tl_errors 2.000s 103.896us 1 1 100.00
tl_d_illegal_access 1 1 100.00
lc_ctrl_tl_errors 2.000s 103.896us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
lc_ctrl_csr_hw_reset 2.000s 36.650us 1 1 100.00
lc_ctrl_csr_rw 1.000s 28.415us 1 1 100.00
lc_ctrl_csr_aliasing 2.000s 33.817us 1 1 100.00
lc_ctrl_same_csr_outstanding 2.000s 162.968us 1 1 100.00
tl_d_partial_access 4 4 100.00
lc_ctrl_csr_hw_reset 2.000s 36.650us 1 1 100.00
lc_ctrl_csr_rw 1.000s 28.415us 1 1 100.00
lc_ctrl_csr_aliasing 2.000s 33.817us 1 1 100.00
lc_ctrl_same_csr_outstanding 2.000s 162.968us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
lc_ctrl_tl_intg_err 3.000s 216.624us 1 1 100.00
lc_ctrl_sec_cm 4.000s 512.381us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
lc_ctrl_tl_intg_err 3.000s 216.624us 1 1 100.00
sec_cm_transition_config_regwen 1 1 100.00
lc_ctrl_regwen_during_op 5.000s 301.929us 1 1 100.00
sec_cm_manuf_state_sparse 2 2 100.00
lc_ctrl_state_failure 4.000s 422.477us 1 1 100.00
lc_ctrl_sec_cm 4.000s 512.381us 1 1 100.00
sec_cm_transition_ctr_sparse 2 2 100.00
lc_ctrl_state_failure 4.000s 422.477us 1 1 100.00
lc_ctrl_sec_cm 4.000s 512.381us 1 1 100.00
sec_cm_manuf_state_bkgn_chk 2 2 100.00
lc_ctrl_state_failure 4.000s 422.477us 1 1 100.00
lc_ctrl_sec_cm 4.000s 512.381us 1 1 100.00
sec_cm_transition_ctr_bkgn_chk 2 2 100.00
lc_ctrl_state_failure 4.000s 422.477us 1 1 100.00
lc_ctrl_sec_cm 4.000s 512.381us 1 1 100.00
sec_cm_state_config_sparse 2 2 100.00
lc_ctrl_state_failure 4.000s 422.477us 1 1 100.00
lc_ctrl_sec_cm 4.000s 512.381us 1 1 100.00
sec_cm_main_fsm_sparse 2 2 100.00
lc_ctrl_state_failure 4.000s 422.477us 1 1 100.00
lc_ctrl_sec_cm 4.000s 512.381us 1 1 100.00
sec_cm_kmac_fsm_sparse 2 2 100.00
lc_ctrl_state_failure 4.000s 422.477us 1 1 100.00
lc_ctrl_sec_cm 4.000s 512.381us 1 1 100.00
sec_cm_main_fsm_local_esc 2 2 100.00
lc_ctrl_state_failure 4.000s 422.477us 1 1 100.00
lc_ctrl_sec_cm 4.000s 512.381us 1 1 100.00
sec_cm_main_fsm_global_esc 1 1 100.00
lc_ctrl_security_escalation 6.000s 348.355us 1 1 100.00
sec_cm_main_ctrl_flow_consistency 2 2 100.00
lc_ctrl_state_post_trans 3.000s 245.016us 1 1 100.00
lc_ctrl_jtag_state_post_trans 5.000s 539.416us 1 1 100.00
sec_cm_intersig_mubi 1 1 100.00
lc_ctrl_sec_mubi 5.000s 265.582us 1 1 100.00
sec_cm_token_valid_ctrl_mubi 1 1 100.00
lc_ctrl_sec_mubi 5.000s 265.582us 1 1 100.00
sec_cm_token_digest 1 1 100.00
lc_ctrl_sec_token_digest 9.000s 4768.163us 1 1 100.00
sec_cm_token_mux_ctrl_redun 1 1 100.00
lc_ctrl_sec_token_mux 6.000s 361.141us 1 1 100.00
sec_cm_token_valid_mux_redun 1 1 100.00
lc_ctrl_sec_token_mux 6.000s 361.141us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 1 1 100.00
lc_ctrl_stress_all_with_rand_reset 22.000s 6112.727us 1 1 100.00