Simulation Results: lc_ctrl/volatile_unlock_enabled

 
06/04/2026 16:07:05 DVSim: v1.17.3 sha: d2f24af json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 92.06 %
  • code
  • 94.06 %
  • assert
  • 95.82 %
  • func
  • 86.31 %
  • block
  • 97.07 %
  • line
  • 97.66 %
  • branch
  • 92.56 %
  • toggle
  • 88.42 %
  • FSM
  • 97.62 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
V3
0.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
lc_ctrl_smoke 2.000s 44.067us 1 1 100.00
csr_hw_reset 1 1 100.00
lc_ctrl_csr_hw_reset 1.000s 18.040us 1 1 100.00
csr_rw 1 1 100.00
lc_ctrl_csr_rw 1.000s 54.029us 1 1 100.00
csr_bit_bash 1 1 100.00
lc_ctrl_csr_bit_bash 1.000s 21.751us 1 1 100.00
csr_aliasing 1 1 100.00
lc_ctrl_csr_aliasing 2.000s 22.782us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
lc_ctrl_csr_mem_rw_with_rand_reset 2.000s 55.329us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
lc_ctrl_csr_rw 1.000s 54.029us 1 1 100.00
lc_ctrl_csr_aliasing 2.000s 22.782us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
state_post_trans 1 1 100.00
lc_ctrl_state_post_trans 3.000s 372.606us 1 1 100.00
regwen_during_op 1 1 100.00
lc_ctrl_regwen_during_op 7.000s 1125.600us 1 1 100.00
rand_wr_claim_transition_if 1 1 100.00
lc_ctrl_claim_transition_if 1.000s 45.429us 1 1 100.00
lc_prog_failure 1 1 100.00
lc_ctrl_prog_failure 2.000s 131.397us 1 1 100.00
lc_state_failure 1 1 100.00
lc_ctrl_state_failure 4.000s 226.076us 1 1 100.00
lc_errors 1 1 100.00
lc_ctrl_errors 5.000s 255.201us 1 1 100.00
security_escalation 7 7 100.00
lc_ctrl_state_failure 4.000s 226.076us 1 1 100.00
lc_ctrl_prog_failure 2.000s 131.397us 1 1 100.00
lc_ctrl_errors 5.000s 255.201us 1 1 100.00
lc_ctrl_security_escalation 4.000s 1104.035us 1 1 100.00
lc_ctrl_jtag_state_failure 22.000s 14103.574us 1 1 100.00
lc_ctrl_jtag_prog_failure 5.000s 3258.713us 1 1 100.00
lc_ctrl_jtag_errors 47.000s 2744.519us 1 1 100.00
jtag_access 13 13 100.00
lc_ctrl_jtag_csr_hw_reset 4.000s 483.384us 1 1 100.00
lc_ctrl_jtag_csr_rw 2.000s 217.894us 1 1 100.00
lc_ctrl_jtag_csr_bit_bash 4.000s 378.282us 1 1 100.00
lc_ctrl_jtag_csr_aliasing 7.000s 859.802us 1 1 100.00
lc_ctrl_jtag_same_csr_outstanding 1.000s 18.673us 1 1 100.00
lc_ctrl_jtag_csr_mem_rw_with_rand_reset 4.000s 291.318us 1 1 100.00
lc_ctrl_jtag_alert_test 2.000s 248.854us 1 1 100.00
lc_ctrl_jtag_smoke 7.000s 294.437us 1 1 100.00
lc_ctrl_jtag_state_post_trans 9.000s 5740.753us 1 1 100.00
lc_ctrl_jtag_prog_failure 5.000s 3258.713us 1 1 100.00
lc_ctrl_jtag_errors 47.000s 2744.519us 1 1 100.00
lc_ctrl_jtag_access 6.000s 2565.800us 1 1 100.00
lc_ctrl_jtag_regwen_during_op 14.000s 3175.909us 1 1 100.00
jtag_priority 1 1 100.00
lc_ctrl_jtag_priority 25.000s 12895.244us 1 1 100.00
lc_ctrl_volatile_unlock 1 1 100.00
lc_ctrl_volatile_unlock_smoke 2.000s 14.530us 1 1 100.00
stress_all 1 1 100.00
lc_ctrl_stress_all 59.000s 31345.797us 1 1 100.00
alert_test 1 1 100.00
lc_ctrl_alert_test 2.000s 27.942us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
lc_ctrl_tl_errors 3.000s 49.322us 1 1 100.00
tl_d_illegal_access 1 1 100.00
lc_ctrl_tl_errors 3.000s 49.322us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
lc_ctrl_csr_hw_reset 1.000s 18.040us 1 1 100.00
lc_ctrl_csr_rw 1.000s 54.029us 1 1 100.00
lc_ctrl_csr_aliasing 2.000s 22.782us 1 1 100.00
lc_ctrl_same_csr_outstanding 2.000s 95.448us 1 1 100.00
tl_d_partial_access 4 4 100.00
lc_ctrl_csr_hw_reset 1.000s 18.040us 1 1 100.00
lc_ctrl_csr_rw 1.000s 54.029us 1 1 100.00
lc_ctrl_csr_aliasing 2.000s 22.782us 1 1 100.00
lc_ctrl_same_csr_outstanding 2.000s 95.448us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
lc_ctrl_tl_intg_err 3.000s 181.273us 1 1 100.00
lc_ctrl_sec_cm 5.000s 947.216us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
lc_ctrl_tl_intg_err 3.000s 181.273us 1 1 100.00
sec_cm_transition_config_regwen 1 1 100.00
lc_ctrl_regwen_during_op 7.000s 1125.600us 1 1 100.00
sec_cm_manuf_state_sparse 2 2 100.00
lc_ctrl_state_failure 4.000s 226.076us 1 1 100.00
lc_ctrl_sec_cm 5.000s 947.216us 1 1 100.00
sec_cm_transition_ctr_sparse 2 2 100.00
lc_ctrl_state_failure 4.000s 226.076us 1 1 100.00
lc_ctrl_sec_cm 5.000s 947.216us 1 1 100.00
sec_cm_manuf_state_bkgn_chk 2 2 100.00
lc_ctrl_state_failure 4.000s 226.076us 1 1 100.00
lc_ctrl_sec_cm 5.000s 947.216us 1 1 100.00
sec_cm_transition_ctr_bkgn_chk 2 2 100.00
lc_ctrl_state_failure 4.000s 226.076us 1 1 100.00
lc_ctrl_sec_cm 5.000s 947.216us 1 1 100.00
sec_cm_state_config_sparse 2 2 100.00
lc_ctrl_state_failure 4.000s 226.076us 1 1 100.00
lc_ctrl_sec_cm 5.000s 947.216us 1 1 100.00
sec_cm_main_fsm_sparse 2 2 100.00
lc_ctrl_state_failure 4.000s 226.076us 1 1 100.00
lc_ctrl_sec_cm 5.000s 947.216us 1 1 100.00
sec_cm_kmac_fsm_sparse 2 2 100.00
lc_ctrl_state_failure 4.000s 226.076us 1 1 100.00
lc_ctrl_sec_cm 5.000s 947.216us 1 1 100.00
sec_cm_main_fsm_local_esc 2 2 100.00
lc_ctrl_state_failure 4.000s 226.076us 1 1 100.00
lc_ctrl_sec_cm 5.000s 947.216us 1 1 100.00
sec_cm_main_fsm_global_esc 1 1 100.00
lc_ctrl_security_escalation 4.000s 1104.035us 1 1 100.00
sec_cm_main_ctrl_flow_consistency 2 2 100.00
lc_ctrl_state_post_trans 3.000s 372.606us 1 1 100.00
lc_ctrl_jtag_state_post_trans 9.000s 5740.753us 1 1 100.00
sec_cm_intersig_mubi 1 1 100.00
lc_ctrl_sec_mubi 5.000s 349.696us 1 1 100.00
sec_cm_token_valid_ctrl_mubi 1 1 100.00
lc_ctrl_sec_mubi 5.000s 349.696us 1 1 100.00
sec_cm_token_digest 1 1 100.00
lc_ctrl_sec_token_digest 6.000s 1630.264us 1 1 100.00
sec_cm_token_mux_ctrl_redun 1 1 100.00
lc_ctrl_sec_token_mux 7.000s 1790.249us 1 1 100.00
sec_cm_token_valid_mux_redun 1 1 100.00
lc_ctrl_sec_token_mux 7.000s 1790.249us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 0 1 0.00
lc_ctrl_stress_all_with_rand_reset 15.000s 1896.744us 0 1 0.00

Error Messages

   Test seed line log context
UVM_ERROR (cip_base_vseq.sv:1237) [lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses.
lc_ctrl_stress_all_with_rand_reset 71553489573756150997387792673922156269308652530622705013125623163605372017507 2814
UVM_ERROR @ 1896744493 ps: (cip_base_vseq.sv:1237) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 1896744493 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---