Simulation Results: otbn

 
06/04/2026 16:07:05 DVSim: v1.17.3 sha: d2f24af json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 94.13 %
  • code
  • 95.12 %
  • assert
  • 89.39 %
  • func
  • 97.88 %
  • block
  • 99.36 %
  • line
  • 99.56 %
  • branch
  • 91.84 %
  • toggle
  • 91.62 %
  • FSM
  • 97.44 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
V3
0.00%
unmapped
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
otbn_smoke 10.000s 80.202us 1 1 100.00
single_binary 1 1 100.00
otbn_single 9.000s 28.265us 1 1 100.00
csr_hw_reset 1 1 100.00
otbn_csr_hw_reset 4.000s 33.617us 1 1 100.00
csr_rw 1 1 100.00
otbn_csr_rw 4.000s 36.365us 1 1 100.00
csr_bit_bash 1 1 100.00
otbn_csr_bit_bash 5.000s 87.929us 1 1 100.00
csr_aliasing 1 1 100.00
otbn_csr_aliasing 4.000s 36.757us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
otbn_csr_mem_rw_with_rand_reset 5.000s 25.899us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
otbn_csr_rw 4.000s 36.365us 1 1 100.00
otbn_csr_aliasing 4.000s 36.757us 1 1 100.00
mem_walk 1 1 100.00
otbn_mem_walk 105.000s 13715.651us 1 1 100.00
mem_partial_access 1 1 100.00
otbn_mem_partial_access 27.000s 3205.297us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
reset_recovery 1 1 100.00
otbn_reset 44.000s 141.811us 1 1 100.00
multi_error 1 1 100.00
otbn_multi_err 57.000s 170.257us 1 1 100.00
back_to_back 1 1 100.00
otbn_multi 27.000s 124.178us 1 1 100.00
stress_all 1 1 100.00
otbn_stress_all 19.000s 314.662us 1 1 100.00
lc_escalation 1 1 100.00
otbn_escalate 5.000s 13.379us 1 1 100.00
zero_state_err_urnd 1 1 100.00
otbn_zero_state_err_urnd 6.000s 39.601us 1 1 100.00
sw_errs_fatal_chk 1 1 100.00
otbn_sw_errs_fatal_chk 5.000s 13.705us 1 1 100.00
alert_test 1 1 100.00
otbn_alert_test 5.000s 26.877us 1 1 100.00
intr_test 1 1 100.00
otbn_intr_test 3.000s 15.167us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
otbn_tl_errors 6.000s 438.974us 1 1 100.00
tl_d_illegal_access 1 1 100.00
otbn_tl_errors 6.000s 438.974us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
otbn_csr_hw_reset 4.000s 33.617us 1 1 100.00
otbn_csr_rw 4.000s 36.365us 1 1 100.00
otbn_csr_aliasing 4.000s 36.757us 1 1 100.00
otbn_same_csr_outstanding 4.000s 22.702us 1 1 100.00
tl_d_partial_access 4 4 100.00
otbn_csr_hw_reset 4.000s 33.617us 1 1 100.00
otbn_csr_rw 4.000s 36.365us 1 1 100.00
otbn_csr_aliasing 4.000s 36.757us 1 1 100.00
otbn_same_csr_outstanding 4.000s 22.702us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
mem_integrity 2 2 100.00
otbn_imem_err 8.000s 27.968us 1 1 100.00
otbn_dmem_err 15.000s 248.985us 1 1 100.00
internal_integrity 4 4 100.00
otbn_alu_bignum_mod_err 8.000s 102.380us 1 1 100.00
otbn_controller_ispr_rdata_err 6.000s 111.187us 1 1 100.00
otbn_mac_bignum_acc_err 6.000s 51.767us 1 1 100.00
otbn_urnd_err 8.000s 53.537us 1 1 100.00
illegal_bus_access 1 1 100.00
otbn_illegal_mem_acc 5.000s 33.410us 1 1 100.00
otbn_mem_gnt_acc_err 1 1 100.00
otbn_mem_gnt_acc_err 13.000s 38.846us 1 1 100.00
otbn_non_sec_partial_wipe 1 1 100.00
otbn_partial_wipe 7.000s 34.676us 1 1 100.00
tl_intg_err 2 2 100.00
otbn_tl_intg_err 14.000s 134.451us 1 1 100.00
otbn_sec_cm 99.000s 570.521us 1 1 100.00
passthru_mem_tl_intg_err 1 1 100.00
otbn_passthru_mem_tl_intg_err 18.000s 384.394us 1 1 100.00
prim_fsm_check 1 1 100.00
otbn_sec_cm 99.000s 570.521us 1 1 100.00
prim_count_check 1 1 100.00
otbn_sec_cm 99.000s 570.521us 1 1 100.00
sec_cm_mem_scramble 1 1 100.00
otbn_smoke 10.000s 80.202us 1 1 100.00
sec_cm_data_mem_integrity 1 1 100.00
otbn_dmem_err 15.000s 248.985us 1 1 100.00
sec_cm_instruction_mem_integrity 1 1 100.00
otbn_imem_err 8.000s 27.968us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
otbn_tl_intg_err 14.000s 134.451us 1 1 100.00
sec_cm_controller_fsm_global_esc 1 1 100.00
otbn_escalate 5.000s 13.379us 1 1 100.00
sec_cm_controller_fsm_local_esc 5 5 100.00
otbn_imem_err 8.000s 27.968us 1 1 100.00
otbn_dmem_err 15.000s 248.985us 1 1 100.00
otbn_zero_state_err_urnd 6.000s 39.601us 1 1 100.00
otbn_illegal_mem_acc 5.000s 33.410us 1 1 100.00
otbn_sec_cm 99.000s 570.521us 1 1 100.00
sec_cm_controller_fsm_sparse 1 1 100.00
otbn_sec_cm 99.000s 570.521us 1 1 100.00
sec_cm_scramble_key_sideload 1 1 100.00
otbn_single 9.000s 28.265us 1 1 100.00
sec_cm_scramble_ctrl_fsm_local_esc 5 5 100.00
otbn_imem_err 8.000s 27.968us 1 1 100.00
otbn_dmem_err 15.000s 248.985us 1 1 100.00
otbn_zero_state_err_urnd 6.000s 39.601us 1 1 100.00
otbn_illegal_mem_acc 5.000s 33.410us 1 1 100.00
otbn_sec_cm 99.000s 570.521us 1 1 100.00
sec_cm_scramble_ctrl_fsm_sparse 1 1 100.00
otbn_sec_cm 99.000s 570.521us 1 1 100.00
sec_cm_start_stop_ctrl_fsm_global_esc 1 1 100.00
otbn_escalate 5.000s 13.379us 1 1 100.00
sec_cm_start_stop_ctrl_fsm_local_esc 5 5 100.00
otbn_imem_err 8.000s 27.968us 1 1 100.00
otbn_dmem_err 15.000s 248.985us 1 1 100.00
otbn_zero_state_err_urnd 6.000s 39.601us 1 1 100.00
otbn_illegal_mem_acc 5.000s 33.410us 1 1 100.00
otbn_sec_cm 99.000s 570.521us 1 1 100.00
sec_cm_start_stop_ctrl_fsm_sparse 1 1 100.00
otbn_sec_cm 99.000s 570.521us 1 1 100.00
sec_cm_data_reg_sw_sca 1 1 100.00
otbn_single 9.000s 28.265us 1 1 100.00
sec_cm_ctrl_redun 1 1 100.00
otbn_ctrl_redun 9.000s 35.269us 1 1 100.00
sec_cm_pc_ctrl_flow_redun 1 1 100.00
otbn_pc_ctrl_flow_redun 5.000s 15.884us 1 1 100.00
sec_cm_rnd_bus_consistency 1 1 100.00
otbn_rnd_sec_cm 36.000s 2108.015us 1 1 100.00
sec_cm_rnd_rng_digest 1 1 100.00
otbn_rnd_sec_cm 36.000s 2108.015us 1 1 100.00
sec_cm_rf_base_data_reg_sw_integrity 1 1 100.00
otbn_rf_base_intg_err 6.000s 46.044us 1 1 100.00
sec_cm_rf_base_data_reg_sw_glitch_detect 1 1 100.00
otbn_sec_cm 99.000s 570.521us 1 1 100.00
sec_cm_stack_wr_ptr_ctr_redun 1 1 100.00
otbn_sec_cm 99.000s 570.521us 1 1 100.00
sec_cm_rf_bignum_data_reg_sw_integrity 1 1 100.00
otbn_rf_bignum_intg_err 8.000s 60.108us 1 1 100.00
sec_cm_rf_bignum_data_reg_sw_glitch_detect 1 1 100.00
otbn_sec_cm 99.000s 570.521us 1 1 100.00
sec_cm_loop_stack_ctr_redun 1 1 100.00
otbn_sec_cm 99.000s 570.521us 1 1 100.00
sec_cm_loop_stack_addr_integrity 1 1 100.00
otbn_stack_addr_integ_chk 5.000s 152.791us 1 1 100.00
sec_cm_call_stack_addr_integrity 1 1 100.00
otbn_stack_addr_integ_chk 5.000s 152.791us 1 1 100.00
sec_cm_start_stop_ctrl_state_consistency 1 1 100.00
otbn_sec_wipe_err 15.000s 40.415us 1 1 100.00
sec_cm_data_mem_sec_wipe 1 1 100.00
otbn_single 9.000s 28.265us 1 1 100.00
sec_cm_instruction_mem_sec_wipe 1 1 100.00
otbn_single 9.000s 28.265us 1 1 100.00
sec_cm_data_reg_sw_sec_wipe 1 1 100.00
otbn_single 9.000s 28.265us 1 1 100.00
sec_cm_write_mem_integrity 1 1 100.00
otbn_multi 27.000s 124.178us 1 1 100.00
sec_cm_ctrl_flow_count 1 1 100.00
otbn_single 9.000s 28.265us 1 1 100.00
sec_cm_ctrl_flow_sca 1 1 100.00
otbn_single 9.000s 28.265us 1 1 100.00
sec_cm_data_mem_sw_noaccess 1 1 100.00
otbn_sw_no_acc 18.000s 55.222us 1 1 100.00
sec_cm_key_sideload 1 1 100.00
otbn_single 9.000s 28.265us 1 1 100.00
sec_cm_tlul_fifo_ctr_redun 1 1 100.00
otbn_sec_cm 99.000s 570.521us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 0 1 0.00
otbn_stress_all_with_rand_reset 62.000s 1055.688us 0 1 0.00
Testpoint Test Max Runtime Sim Time Pass Total %
Unmapped 1 1 100.00
otbn_smoke_vectorized 6.000s 82.816us 1 1 100.00

Error Messages

   Test seed line log context
UVM_FATAL (otbn_base_vseq.sv:348) [otbn_dmem_err_vseq] Check failed (!cfg.under_reset)
otbn_stress_all_with_rand_reset 111749304239827223600198159232886758997971841668630691467276457575583004695516 236
UVM_FATAL @ 1055687743 ps: (otbn_base_vseq.sv:348) [uvm_test_top.env.virtual_sequencer.otbn_dmem_err_vseq] Check failed (!cfg.under_reset)
UVM_INFO @ 1055687743 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---