| V1 |
|
0.00% |
| V2 |
|
0.00% |
| V2S |
|
0.00% |
| V3 |
|
0.00% |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| wake_up | 0 | 1 | 0.00 | |||
| otp_ctrl_wake_up | 4.000s | 209.120us | 0 | 1 | 0.00 | |
| smoke | 0 | 1 | 0.00 | |||
| otp_ctrl_smoke | 4.000s | 641.179us | 0 | 1 | 0.00 | |
| csr_hw_reset | 0 | 1 | 0.00 | |||
| otp_ctrl_csr_hw_reset | 3.000s | 238.596us | 0 | 1 | 0.00 | |
| csr_rw | 0 | 1 | 0.00 | |||
| otp_ctrl_csr_rw | 3.000s | 130.167us | 0 | 1 | 0.00 | |
| csr_bit_bash | 0 | 1 | 0.00 | |||
| otp_ctrl_csr_bit_bash | 7.000s | 136.410us | 0 | 1 | 0.00 | |
| csr_aliasing | 0 | 1 | 0.00 | |||
| otp_ctrl_csr_aliasing | 12.000s | 1618.517us | 0 | 1 | 0.00 | |
| csr_mem_rw_with_rand_reset | 0 | 1 | 0.00 | |||
| otp_ctrl_csr_mem_rw_with_rand_reset | 5.000s | 1181.688us | 0 | 1 | 0.00 | |
| regwen_csr_and_corresponding_lockable_csr | 0 | 2 | 0.00 | |||
| otp_ctrl_csr_rw | 3.000s | 130.167us | 0 | 1 | 0.00 | |
| otp_ctrl_csr_aliasing | 12.000s | 1618.517us | 0 | 1 | 0.00 | |
| mem_walk | 0 | 1 | 0.00 | |||
| otp_ctrl_mem_walk | 2.000s | 116.859us | 0 | 1 | 0.00 | |
| mem_partial_access | 0 | 1 | 0.00 | |||
| otp_ctrl_mem_partial_access | 2.000s | 92.426us | 0 | 1 | 0.00 | |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| dai_access_partition_walk | 0 | 1 | 0.00 | |||
| otp_ctrl_partition_walk | 135.000s | 2403.051us | 0 | 1 | 0.00 | |
| init_fail | 0 | 1 | 0.00 | |||
| otp_ctrl_init_fail | 5.000s | 113.419us | 0 | 1 | 0.00 | |
| partition_check | 0 | 2 | 0.00 | |||
| otp_ctrl_background_chks | 9.000s | 304.902us | 0 | 1 | 0.00 | |
| otp_ctrl_check_fail | 6.000s | 89.152us | 0 | 1 | 0.00 | |
| regwen_during_otp_init | 0 | 1 | 0.00 | |||
| otp_ctrl_regwen | 8.000s | 791.822us | 0 | 1 | 0.00 | |
| partition_lock | 0 | 1 | 0.00 | |||
| otp_ctrl_dai_lock | 10.000s | 5279.185us | 0 | 1 | 0.00 | |
| interface_key_check | 0 | 1 | 0.00 | |||
| otp_ctrl_parallel_key_req | 8.000s | 354.922us | 0 | 1 | 0.00 | |
| lc_interactions | 0 | 2 | 0.00 | |||
| otp_ctrl_parallel_lc_req | 10.000s | 377.032us | 0 | 1 | 0.00 | |
| otp_ctrl_parallel_lc_esc | 4.000s | 142.345us | 0 | 1 | 0.00 | |
| otp_dai_errors | 0 | 1 | 0.00 | |||
| otp_ctrl_dai_errs | 623.000s | 20262.914us | 0 | 1 | 0.00 | |
| otp_macro_errors | 0 | 1 | 0.00 | |||
| otp_ctrl_macro_errs | 1346.000s | 20050.689us | 0 | 1 | 0.00 | |
| test_access | 0 | 1 | 0.00 | |||
| otp_ctrl_test_access | 11.000s | 401.996us | 0 | 1 | 0.00 | |
| stress_all | 0 | 1 | 0.00 | |||
| otp_ctrl_stress_all | 8.000s | 268.069us | 0 | 1 | 0.00 | |
| intr_test | 0 | 1 | 0.00 | |||
| otp_ctrl_intr_test | 2.000s | 85.220us | 0 | 1 | 0.00 | |
| alert_test | 0 | 1 | 0.00 | |||
| otp_ctrl_alert_test | 4.000s | 79.065us | 0 | 1 | 0.00 | |
| tl_d_oob_addr_access | 0 | 1 | 0.00 | |||
| otp_ctrl_tl_errors | 4.000s | 190.107us | 0 | 1 | 0.00 | |
| tl_d_illegal_access | 0 | 1 | 0.00 | |||
| otp_ctrl_tl_errors | 4.000s | 190.107us | 0 | 1 | 0.00 | |
| tl_d_outstanding_access | 0 | 4 | 0.00 | |||
| otp_ctrl_csr_hw_reset | 3.000s | 238.596us | 0 | 1 | 0.00 | |
| otp_ctrl_csr_rw | 3.000s | 130.167us | 0 | 1 | 0.00 | |
| otp_ctrl_csr_aliasing | 12.000s | 1618.517us | 0 | 1 | 0.00 | |
| otp_ctrl_same_csr_outstanding | 6.000s | 1560.963us | 0 | 1 | 0.00 | |
| tl_d_partial_access | 0 | 4 | 0.00 | |||
| otp_ctrl_csr_hw_reset | 3.000s | 238.596us | 0 | 1 | 0.00 | |
| otp_ctrl_csr_rw | 3.000s | 130.167us | 0 | 1 | 0.00 | |
| otp_ctrl_csr_aliasing | 12.000s | 1618.517us | 0 | 1 | 0.00 | |
| otp_ctrl_same_csr_outstanding | 6.000s | 1560.963us | 0 | 1 | 0.00 | |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| sec_cm_additional_check | 0 | 1 | 0.00 | |||
| otp_ctrl_sec_cm | 416.000s | 20032.505us | 0 | 1 | 0.00 | |
| tl_intg_err | 0 | 2 | 0.00 | |||
| otp_ctrl_tl_intg_err | 11.000s | 1315.920us | 0 | 1 | 0.00 | |
| otp_ctrl_sec_cm | 416.000s | 20032.505us | 0 | 1 | 0.00 | |
| prim_count_check | 0 | 1 | 0.00 | |||
| otp_ctrl_sec_cm | 416.000s | 20032.505us | 0 | 1 | 0.00 | |
| prim_fsm_check | 0 | 1 | 0.00 | |||
| otp_ctrl_sec_cm | 416.000s | 20032.505us | 0 | 1 | 0.00 | |
| sec_cm_bus_integrity | 0 | 1 | 0.00 | |||
| otp_ctrl_tl_intg_err | 11.000s | 1315.920us | 0 | 1 | 0.00 | |
| sec_cm_secret_mem_scramble | 0 | 1 | 0.00 | |||
| otp_ctrl_smoke | 4.000s | 641.179us | 0 | 1 | 0.00 | |
| sec_cm_part_mem_digest | 0 | 1 | 0.00 | |||
| otp_ctrl_smoke | 4.000s | 641.179us | 0 | 1 | 0.00 | |
| sec_cm_dai_fsm_sparse | 0 | 1 | 0.00 | |||
| otp_ctrl_sec_cm | 416.000s | 20032.505us | 0 | 1 | 0.00 | |
| sec_cm_kdi_fsm_sparse | 0 | 1 | 0.00 | |||
| otp_ctrl_sec_cm | 416.000s | 20032.505us | 0 | 1 | 0.00 | |
| sec_cm_lci_fsm_sparse | 0 | 1 | 0.00 | |||
| otp_ctrl_sec_cm | 416.000s | 20032.505us | 0 | 1 | 0.00 | |
| sec_cm_part_fsm_sparse | 0 | 1 | 0.00 | |||
| otp_ctrl_sec_cm | 416.000s | 20032.505us | 0 | 1 | 0.00 | |
| sec_cm_scrmbl_fsm_sparse | 0 | 1 | 0.00 | |||
| otp_ctrl_sec_cm | 416.000s | 20032.505us | 0 | 1 | 0.00 | |
| sec_cm_timer_fsm_sparse | 0 | 1 | 0.00 | |||
| otp_ctrl_sec_cm | 416.000s | 20032.505us | 0 | 1 | 0.00 | |
| sec_cm_dai_ctr_redun | 0 | 1 | 0.00 | |||
| otp_ctrl_sec_cm | 416.000s | 20032.505us | 0 | 1 | 0.00 | |
| sec_cm_kdi_seed_ctr_redun | 0 | 1 | 0.00 | |||
| otp_ctrl_sec_cm | 416.000s | 20032.505us | 0 | 1 | 0.00 | |
| sec_cm_kdi_entropy_ctr_redun | 0 | 1 | 0.00 | |||
| otp_ctrl_sec_cm | 416.000s | 20032.505us | 0 | 1 | 0.00 | |
| sec_cm_lci_ctr_redun | 0 | 1 | 0.00 | |||
| otp_ctrl_sec_cm | 416.000s | 20032.505us | 0 | 1 | 0.00 | |
| sec_cm_part_ctr_redun | 0 | 1 | 0.00 | |||
| otp_ctrl_sec_cm | 416.000s | 20032.505us | 0 | 1 | 0.00 | |
| sec_cm_scrmbl_ctr_redun | 0 | 1 | 0.00 | |||
| otp_ctrl_sec_cm | 416.000s | 20032.505us | 0 | 1 | 0.00 | |
| sec_cm_timer_integ_ctr_redun | 0 | 1 | 0.00 | |||
| otp_ctrl_sec_cm | 416.000s | 20032.505us | 0 | 1 | 0.00 | |
| sec_cm_timer_cnsty_ctr_redun | 0 | 1 | 0.00 | |||
| otp_ctrl_sec_cm | 416.000s | 20032.505us | 0 | 1 | 0.00 | |
| sec_cm_timer_lfsr_redun | 0 | 1 | 0.00 | |||
| otp_ctrl_sec_cm | 416.000s | 20032.505us | 0 | 1 | 0.00 | |
| sec_cm_dai_fsm_local_esc | 0 | 2 | 0.00 | |||
| otp_ctrl_parallel_lc_esc | 4.000s | 142.345us | 0 | 1 | 0.00 | |
| otp_ctrl_sec_cm | 416.000s | 20032.505us | 0 | 1 | 0.00 | |
| sec_cm_lci_fsm_local_esc | 0 | 1 | 0.00 | |||
| otp_ctrl_parallel_lc_esc | 4.000s | 142.345us | 0 | 1 | 0.00 | |
| sec_cm_kdi_fsm_local_esc | 0 | 1 | 0.00 | |||
| otp_ctrl_parallel_lc_esc | 4.000s | 142.345us | 0 | 1 | 0.00 | |
| sec_cm_part_fsm_local_esc | 0 | 2 | 0.00 | |||
| otp_ctrl_parallel_lc_esc | 4.000s | 142.345us | 0 | 1 | 0.00 | |
| otp_ctrl_macro_errs | 1346.000s | 20050.689us | 0 | 1 | 0.00 | |
| sec_cm_scrmbl_fsm_local_esc | 0 | 1 | 0.00 | |||
| otp_ctrl_parallel_lc_esc | 4.000s | 142.345us | 0 | 1 | 0.00 | |
| sec_cm_timer_fsm_local_esc | 0 | 2 | 0.00 | |||
| otp_ctrl_parallel_lc_esc | 4.000s | 142.345us | 0 | 1 | 0.00 | |
| otp_ctrl_sec_cm | 416.000s | 20032.505us | 0 | 1 | 0.00 | |
| sec_cm_dai_fsm_global_esc | 0 | 2 | 0.00 | |||
| otp_ctrl_parallel_lc_esc | 4.000s | 142.345us | 0 | 1 | 0.00 | |
| otp_ctrl_sec_cm | 416.000s | 20032.505us | 0 | 1 | 0.00 | |
| sec_cm_lci_fsm_global_esc | 0 | 1 | 0.00 | |||
| otp_ctrl_parallel_lc_esc | 4.000s | 142.345us | 0 | 1 | 0.00 | |
| sec_cm_kdi_fsm_global_esc | 0 | 1 | 0.00 | |||
| otp_ctrl_parallel_lc_esc | 4.000s | 142.345us | 0 | 1 | 0.00 | |
| sec_cm_part_fsm_global_esc | 0 | 2 | 0.00 | |||
| otp_ctrl_parallel_lc_esc | 4.000s | 142.345us | 0 | 1 | 0.00 | |
| otp_ctrl_macro_errs | 1346.000s | 20050.689us | 0 | 1 | 0.00 | |
| sec_cm_scrmbl_fsm_global_esc | 0 | 1 | 0.00 | |||
| otp_ctrl_parallel_lc_esc | 4.000s | 142.345us | 0 | 1 | 0.00 | |
| sec_cm_timer_fsm_global_esc | 0 | 2 | 0.00 | |||
| otp_ctrl_parallel_lc_esc | 4.000s | 142.345us | 0 | 1 | 0.00 | |
| otp_ctrl_sec_cm | 416.000s | 20032.505us | 0 | 1 | 0.00 | |
| sec_cm_part_data_reg_integrity | 0 | 1 | 0.00 | |||
| otp_ctrl_init_fail | 5.000s | 113.419us | 0 | 1 | 0.00 | |
| sec_cm_part_data_reg_bkgn_chk | 0 | 1 | 0.00 | |||
| otp_ctrl_check_fail | 6.000s | 89.152us | 0 | 1 | 0.00 | |
| sec_cm_part_mem_regren | 0 | 1 | 0.00 | |||
| otp_ctrl_dai_lock | 10.000s | 5279.185us | 0 | 1 | 0.00 | |
| sec_cm_part_mem_sw_unreadable | 0 | 1 | 0.00 | |||
| otp_ctrl_dai_lock | 10.000s | 5279.185us | 0 | 1 | 0.00 | |
| sec_cm_part_mem_sw_unwritable | 0 | 1 | 0.00 | |||
| otp_ctrl_dai_lock | 10.000s | 5279.185us | 0 | 1 | 0.00 | |
| sec_cm_lc_part_mem_sw_noaccess | 0 | 1 | 0.00 | |||
| otp_ctrl_dai_lock | 10.000s | 5279.185us | 0 | 1 | 0.00 | |
| sec_cm_access_ctrl_mubi | 0 | 1 | 0.00 | |||
| otp_ctrl_dai_lock | 10.000s | 5279.185us | 0 | 1 | 0.00 | |
| sec_cm_token_valid_ctrl_mubi | 0 | 1 | 0.00 | |||
| otp_ctrl_smoke | 4.000s | 641.179us | 0 | 1 | 0.00 | |
| sec_cm_lc_ctrl_intersig_mubi | 0 | 1 | 0.00 | |||
| otp_ctrl_dai_lock | 10.000s | 5279.185us | 0 | 1 | 0.00 | |
| sec_cm_test_bus_lc_gated | 0 | 1 | 0.00 | |||
| otp_ctrl_smoke | 4.000s | 641.179us | 0 | 1 | 0.00 | |
| sec_cm_test_tl_lc_gate_fsm_sparse | 0 | 1 | 0.00 | |||
| otp_ctrl_sec_cm | 416.000s | 20032.505us | 0 | 1 | 0.00 | |
| sec_cm_direct_access_config_regwen | 0 | 1 | 0.00 | |||
| otp_ctrl_regwen | 8.000s | 791.822us | 0 | 1 | 0.00 | |
| sec_cm_check_trigger_config_regwen | 0 | 1 | 0.00 | |||
| otp_ctrl_smoke | 4.000s | 641.179us | 0 | 1 | 0.00 | |
| sec_cm_check_config_regwen | 0 | 1 | 0.00 | |||
| otp_ctrl_smoke | 4.000s | 641.179us | 0 | 1 | 0.00 | |
| sec_cm_macro_mem_integrity | 0 | 1 | 0.00 | |||
| otp_ctrl_macro_errs | 1346.000s | 20050.689us | 0 | 1 | 0.00 | |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| otp_ctrl_low_freq_read | 0 | 1 | 0.00 | |||
| otp_ctrl_low_freq_read | 83.000s | 59183.027us | 0 | 1 | 0.00 | |
| stress_all_with_rand_reset | 0 | 1 | 0.00 | |||
| otp_ctrl_stress_all_with_rand_reset | 2.000s | 31.238us | 0 | 1 | 0.00 | |
| Test | seed | line | log context | |
|---|---|---|---|---|
| xmsim: *E,COVITS: Covergroup instance unbuf_err_code_cg (/nightly/current_run/scratch/master/otp_ctrl-sim-xcelium/cover_reg_top/fusesoc-work/src/lowrisc_darjeeling_dv_otp_ctrl_env_*/otp_ctrl_env_cov.sv:12) with 'unbuf_err_code_cg_wrap[]' as the instance name will not be saved to the database and its coverage will be merged with another covergroup instance unbuf_err_code_cg (/nightly/current_run/scratch/master/otp_ctrl-sim-xcelium/cover_reg_top/fusesoc-work/src/lowrisc_darjeeling_dv_otp_ctrl_env_*/otp_ctrl_env_cov.sv:12) with the same instance name 'unbuf_err_code_cg_wrap[]'. This is because both the covergroup instances are having same description and are defined in the same scope with the same name. | ||||
| otp_ctrl_tl_errors | 107015917309034858952263794602454844603699467873846475508934339228946413169295 | 192 |
xmsim: *E,COVITS: Covergroup instance unbuf_err_code_cg (/nightly/current_run/scratch/master/otp_ctrl-sim-xcelium/cover_reg_top/fusesoc-work/src/lowrisc_darjeeling_dv_otp_ctrl_env_0.1/otp_ctrl_env_cov.sv:12) with 'unbuf_err_code_cg_wrap[]' as the instance name will not be saved to the database and its coverage will be merged with another covergroup instance unbuf_err_code_cg (/nightly/current_run/scratch/master/otp_ctrl-sim-xcelium/cover_reg_top/fusesoc-work/src/lowrisc_darjeeling_dv_otp_ctrl_env_0.1/otp_ctrl_env_cov.sv:12) with the same instance name 'unbuf_err_code_cg_wrap[]'. This is because both the covergroup instances are having same description and are defined in the same scope with the same name.
xmsim: *E,COVITS: Covergroup instance unbuf_err_code_cg (/nightly/current_run/scratch/master/otp_ctrl-sim-xcelium/cover_reg_top/fusesoc-work/src/lowrisc_darjeeling_dv_otp_ctrl_env_0.1/otp_ctrl_env_cov.sv:12) with 'unbuf_err_code_cg_wrap[]' as the instance name will not be saved to the database and its coverage will be merged with another covergroup instance unbuf_err_code_cg (/nightly/current_run/scratch/master/otp_ctrl-sim-xcelium/cover_reg_top/fusesoc-work/src/lowrisc_darjeeling_dv_otp_ctrl_env_0.1/otp_ctrl_env_cov.sv:12) with the same instance name 'unbuf_err_code_cg_wrap[]'. This is because both the covergroup instances are having same description and are defined in the same scope with the same name.
xmsim: *E,COVITS: Covergroup instance unbuf_err_code_cg (/nightly/current_run/scratch/master/otp_ctrl-sim-xcelium/cover_reg_top/fusesoc-work/src/lowrisc_darjeeling_dv_otp_ctrl_env_0.1/otp_ctrl_env_cov.sv:12) with 'unbuf_err_code_cg_wrap[]' as the instance name will not be saved to the database and its coverage will be merged with another covergroup instance unbuf_err_code_cg (/nightly/current_run/scratch/master/otp_ctrl-sim-xcelium/cover_reg_top/fusesoc-work/src/lowrisc_darjeeling_dv_otp_ctrl_env_0.1/otp_ctrl_env_cov.sv:12) with the same instance name 'unbuf_err_code_cg_wrap[]'. This is because both the covergroup instances are having same description and are defined in the same scope with the same name.
xmsim: *W,CGPIZE: Instance coverage for covergroup instance "lc_esc_en_condition_cg_inst" will not be dumped to database as per_instance option value is set to 0:/nightly/current_run/scratch/master/otp_ctrl-sim-xcelium/cover_reg_top/fusesoc-work/src/lowrisc_darjeeling_dv_otp_ctrl_cov_0/otp_ctrl_cov_if.sv, 71.
xmsim: *W,CGPIZE: Instance coverage for covergroup instance "sram_0_req_condition_cg_inst" will not be dumped to database as per_instance option value is set to 0:/nightly/current_run/scratch/master/otp_ctrl-sim-xcelium/cover_reg_top/fusesoc-work/src/lowrisc_darjeeling_dv_otp_ctrl_cov_0/otp_ctrl_cov_if.sv, 72.
|
|
| otp_ctrl_tl_intg_err | 81891758590491000787589436713043597511872427561789426743905598638758502916654 | 356 |
xmsim: *E,COVITS: Covergroup instance unbuf_err_code_cg (/nightly/current_run/scratch/master/otp_ctrl-sim-xcelium/cover_reg_top/fusesoc-work/src/lowrisc_darjeeling_dv_otp_ctrl_env_0.1/otp_ctrl_env_cov.sv:12) with 'unbuf_err_code_cg_wrap[]' as the instance name will not be saved to the database and its coverage will be merged with another covergroup instance unbuf_err_code_cg (/nightly/current_run/scratch/master/otp_ctrl-sim-xcelium/cover_reg_top/fusesoc-work/src/lowrisc_darjeeling_dv_otp_ctrl_env_0.1/otp_ctrl_env_cov.sv:12) with the same instance name 'unbuf_err_code_cg_wrap[]'. This is because both the covergroup instances are having same description and are defined in the same scope with the same name.
xmsim: *E,COVITS: Covergroup instance unbuf_err_code_cg (/nightly/current_run/scratch/master/otp_ctrl-sim-xcelium/cover_reg_top/fusesoc-work/src/lowrisc_darjeeling_dv_otp_ctrl_env_0.1/otp_ctrl_env_cov.sv:12) with 'unbuf_err_code_cg_wrap[]' as the instance name will not be saved to the database and its coverage will be merged with another covergroup instance unbuf_err_code_cg (/nightly/current_run/scratch/master/otp_ctrl-sim-xcelium/cover_reg_top/fusesoc-work/src/lowrisc_darjeeling_dv_otp_ctrl_env_0.1/otp_ctrl_env_cov.sv:12) with the same instance name 'unbuf_err_code_cg_wrap[]'. This is because both the covergroup instances are having same description and are defined in the same scope with the same name.
xmsim: *E,COVITS: Covergroup instance unbuf_err_code_cg (/nightly/current_run/scratch/master/otp_ctrl-sim-xcelium/cover_reg_top/fusesoc-work/src/lowrisc_darjeeling_dv_otp_ctrl_env_0.1/otp_ctrl_env_cov.sv:12) with 'unbuf_err_code_cg_wrap[]' as the instance name will not be saved to the database and its coverage will be merged with another covergroup instance unbuf_err_code_cg (/nightly/current_run/scratch/master/otp_ctrl-sim-xcelium/cover_reg_top/fusesoc-work/src/lowrisc_darjeeling_dv_otp_ctrl_env_0.1/otp_ctrl_env_cov.sv:12) with the same instance name 'unbuf_err_code_cg_wrap[]'. This is because both the covergroup instances are having same description and are defined in the same scope with the same name.
xmsim: *W,CGPIZE: Instance coverage for covergroup instance "lc_esc_en_condition_cg_inst" will not be dumped to database as per_instance option value is set to 0:/nightly/current_run/scratch/master/otp_ctrl-sim-xcelium/cover_reg_top/fusesoc-work/src/lowrisc_darjeeling_dv_otp_ctrl_cov_0/otp_ctrl_cov_if.sv, 71.
xmsim: *W,CGPIZE: Instance coverage for covergroup instance "sram_0_req_condition_cg_inst" will not be dumped to database as per_instance option value is set to 0:/nightly/current_run/scratch/master/otp_ctrl-sim-xcelium/cover_reg_top/fusesoc-work/src/lowrisc_darjeeling_dv_otp_ctrl_cov_0/otp_ctrl_cov_if.sv, 72.
|
|
| otp_ctrl_intr_test | 61222750532044482100844099829527637625568647867083068452502580153256135529591 | 271 |
xmsim: *E,COVITS: Covergroup instance unbuf_err_code_cg (/nightly/current_run/scratch/master/otp_ctrl-sim-xcelium/cover_reg_top/fusesoc-work/src/lowrisc_darjeeling_dv_otp_ctrl_env_0.1/otp_ctrl_env_cov.sv:12) with 'unbuf_err_code_cg_wrap[]' as the instance name will not be saved to the database and its coverage will be merged with another covergroup instance unbuf_err_code_cg (/nightly/current_run/scratch/master/otp_ctrl-sim-xcelium/cover_reg_top/fusesoc-work/src/lowrisc_darjeeling_dv_otp_ctrl_env_0.1/otp_ctrl_env_cov.sv:12) with the same instance name 'unbuf_err_code_cg_wrap[]'. This is because both the covergroup instances are having same description and are defined in the same scope with the same name.
xmsim: *E,COVITS: Covergroup instance unbuf_err_code_cg (/nightly/current_run/scratch/master/otp_ctrl-sim-xcelium/cover_reg_top/fusesoc-work/src/lowrisc_darjeeling_dv_otp_ctrl_env_0.1/otp_ctrl_env_cov.sv:12) with 'unbuf_err_code_cg_wrap[]' as the instance name will not be saved to the database and its coverage will be merged with another covergroup instance unbuf_err_code_cg (/nightly/current_run/scratch/master/otp_ctrl-sim-xcelium/cover_reg_top/fusesoc-work/src/lowrisc_darjeeling_dv_otp_ctrl_env_0.1/otp_ctrl_env_cov.sv:12) with the same instance name 'unbuf_err_code_cg_wrap[]'. This is because both the covergroup instances are having same description and are defined in the same scope with the same name.
xmsim: *E,COVITS: Covergroup instance unbuf_err_code_cg (/nightly/current_run/scratch/master/otp_ctrl-sim-xcelium/cover_reg_top/fusesoc-work/src/lowrisc_darjeeling_dv_otp_ctrl_env_0.1/otp_ctrl_env_cov.sv:12) with 'unbuf_err_code_cg_wrap[]' as the instance name will not be saved to the database and its coverage will be merged with another covergroup instance unbuf_err_code_cg (/nightly/current_run/scratch/master/otp_ctrl-sim-xcelium/cover_reg_top/fusesoc-work/src/lowrisc_darjeeling_dv_otp_ctrl_env_0.1/otp_ctrl_env_cov.sv:12) with the same instance name 'unbuf_err_code_cg_wrap[]'. This is because both the covergroup instances are having same description and are defined in the same scope with the same name.
xmsim: *W,CGPIZE: Instance coverage for covergroup instance "lc_esc_en_condition_cg_inst" will not be dumped to database as per_instance option value is set to 0:/nightly/current_run/scratch/master/otp_ctrl-sim-xcelium/cover_reg_top/fusesoc-work/src/lowrisc_darjeeling_dv_otp_ctrl_cov_0/otp_ctrl_cov_if.sv, 71.
xmsim: *W,CGPIZE: Instance coverage for covergroup instance "sram_0_req_condition_cg_inst" will not be dumped to database as per_instance option value is set to 0:/nightly/current_run/scratch/master/otp_ctrl-sim-xcelium/cover_reg_top/fusesoc-work/src/lowrisc_darjeeling_dv_otp_ctrl_cov_0/otp_ctrl_cov_if.sv, 72.
|
|
| otp_ctrl_mem_walk | 71573824343370469936912555252627408998982789985658953640527524715070966281298 | 201 |
xmsim: *E,COVITS: Covergroup instance unbuf_err_code_cg (/nightly/current_run/scratch/master/otp_ctrl-sim-xcelium/cover_reg_top/fusesoc-work/src/lowrisc_darjeeling_dv_otp_ctrl_env_0.1/otp_ctrl_env_cov.sv:12) with 'unbuf_err_code_cg_wrap[]' as the instance name will not be saved to the database and its coverage will be merged with another covergroup instance unbuf_err_code_cg (/nightly/current_run/scratch/master/otp_ctrl-sim-xcelium/cover_reg_top/fusesoc-work/src/lowrisc_darjeeling_dv_otp_ctrl_env_0.1/otp_ctrl_env_cov.sv:12) with the same instance name 'unbuf_err_code_cg_wrap[]'. This is because both the covergroup instances are having same description and are defined in the same scope with the same name.
xmsim: *E,COVITS: Covergroup instance unbuf_err_code_cg (/nightly/current_run/scratch/master/otp_ctrl-sim-xcelium/cover_reg_top/fusesoc-work/src/lowrisc_darjeeling_dv_otp_ctrl_env_0.1/otp_ctrl_env_cov.sv:12) with 'unbuf_err_code_cg_wrap[]' as the instance name will not be saved to the database and its coverage will be merged with another covergroup instance unbuf_err_code_cg (/nightly/current_run/scratch/master/otp_ctrl-sim-xcelium/cover_reg_top/fusesoc-work/src/lowrisc_darjeeling_dv_otp_ctrl_env_0.1/otp_ctrl_env_cov.sv:12) with the same instance name 'unbuf_err_code_cg_wrap[]'. This is because both the covergroup instances are having same description and are defined in the same scope with the same name.
xmsim: *E,COVITS: Covergroup instance unbuf_err_code_cg (/nightly/current_run/scratch/master/otp_ctrl-sim-xcelium/cover_reg_top/fusesoc-work/src/lowrisc_darjeeling_dv_otp_ctrl_env_0.1/otp_ctrl_env_cov.sv:12) with 'unbuf_err_code_cg_wrap[]' as the instance name will not be saved to the database and its coverage will be merged with another covergroup instance unbuf_err_code_cg (/nightly/current_run/scratch/master/otp_ctrl-sim-xcelium/cover_reg_top/fusesoc-work/src/lowrisc_darjeeling_dv_otp_ctrl_env_0.1/otp_ctrl_env_cov.sv:12) with the same instance name 'unbuf_err_code_cg_wrap[]'. This is because both the covergroup instances are having same description and are defined in the same scope with the same name.
xmsim: *W,CGPIZE: Instance coverage for covergroup instance "lc_esc_en_condition_cg_inst" will not be dumped to database as per_instance option value is set to 0:/nightly/current_run/scratch/master/otp_ctrl-sim-xcelium/cover_reg_top/fusesoc-work/src/lowrisc_darjeeling_dv_otp_ctrl_cov_0/otp_ctrl_cov_if.sv, 71.
xmsim: *W,CGPIZE: Instance coverage for covergroup instance "sram_0_req_condition_cg_inst" will not be dumped to database as per_instance option value is set to 0:/nightly/current_run/scratch/master/otp_ctrl-sim-xcelium/cover_reg_top/fusesoc-work/src/lowrisc_darjeeling_dv_otp_ctrl_cov_0/otp_ctrl_cov_if.sv, 72.
|
|
| otp_ctrl_mem_partial_access | 26375803758437676747309636131450415768592868570051981331085196044759196137487 | 187 |
xmsim: *E,COVITS: Covergroup instance unbuf_err_code_cg (/nightly/current_run/scratch/master/otp_ctrl-sim-xcelium/cover_reg_top/fusesoc-work/src/lowrisc_darjeeling_dv_otp_ctrl_env_0.1/otp_ctrl_env_cov.sv:12) with 'unbuf_err_code_cg_wrap[]' as the instance name will not be saved to the database and its coverage will be merged with another covergroup instance unbuf_err_code_cg (/nightly/current_run/scratch/master/otp_ctrl-sim-xcelium/cover_reg_top/fusesoc-work/src/lowrisc_darjeeling_dv_otp_ctrl_env_0.1/otp_ctrl_env_cov.sv:12) with the same instance name 'unbuf_err_code_cg_wrap[]'. This is because both the covergroup instances are having same description and are defined in the same scope with the same name.
xmsim: *E,COVITS: Covergroup instance unbuf_err_code_cg (/nightly/current_run/scratch/master/otp_ctrl-sim-xcelium/cover_reg_top/fusesoc-work/src/lowrisc_darjeeling_dv_otp_ctrl_env_0.1/otp_ctrl_env_cov.sv:12) with 'unbuf_err_code_cg_wrap[]' as the instance name will not be saved to the database and its coverage will be merged with another covergroup instance unbuf_err_code_cg (/nightly/current_run/scratch/master/otp_ctrl-sim-xcelium/cover_reg_top/fusesoc-work/src/lowrisc_darjeeling_dv_otp_ctrl_env_0.1/otp_ctrl_env_cov.sv:12) with the same instance name 'unbuf_err_code_cg_wrap[]'. This is because both the covergroup instances are having same description and are defined in the same scope with the same name.
xmsim: *E,COVITS: Covergroup instance unbuf_err_code_cg (/nightly/current_run/scratch/master/otp_ctrl-sim-xcelium/cover_reg_top/fusesoc-work/src/lowrisc_darjeeling_dv_otp_ctrl_env_0.1/otp_ctrl_env_cov.sv:12) with 'unbuf_err_code_cg_wrap[]' as the instance name will not be saved to the database and its coverage will be merged with another covergroup instance unbuf_err_code_cg (/nightly/current_run/scratch/master/otp_ctrl-sim-xcelium/cover_reg_top/fusesoc-work/src/lowrisc_darjeeling_dv_otp_ctrl_env_0.1/otp_ctrl_env_cov.sv:12) with the same instance name 'unbuf_err_code_cg_wrap[]'. This is because both the covergroup instances are having same description and are defined in the same scope with the same name.
xmsim: *W,CGPIZE: Instance coverage for covergroup instance "lc_esc_en_condition_cg_inst" will not be dumped to database as per_instance option value is set to 0:/nightly/current_run/scratch/master/otp_ctrl-sim-xcelium/cover_reg_top/fusesoc-work/src/lowrisc_darjeeling_dv_otp_ctrl_cov_0/otp_ctrl_cov_if.sv, 71.
xmsim: *W,CGPIZE: Instance coverage for covergroup instance "sram_0_req_condition_cg_inst" will not be dumped to database as per_instance option value is set to 0:/nightly/current_run/scratch/master/otp_ctrl-sim-xcelium/cover_reg_top/fusesoc-work/src/lowrisc_darjeeling_dv_otp_ctrl_cov_0/otp_ctrl_cov_if.sv, 72.
|
|
| otp_ctrl_csr_hw_reset | 75865373101750961782080748693532923082906881747339438526121751019623048111328 | 197 |
xmsim: *E,COVITS: Covergroup instance unbuf_err_code_cg (/nightly/current_run/scratch/master/otp_ctrl-sim-xcelium/cover_reg_top/fusesoc-work/src/lowrisc_darjeeling_dv_otp_ctrl_env_0.1/otp_ctrl_env_cov.sv:12) with 'unbuf_err_code_cg_wrap[]' as the instance name will not be saved to the database and its coverage will be merged with another covergroup instance unbuf_err_code_cg (/nightly/current_run/scratch/master/otp_ctrl-sim-xcelium/cover_reg_top/fusesoc-work/src/lowrisc_darjeeling_dv_otp_ctrl_env_0.1/otp_ctrl_env_cov.sv:12) with the same instance name 'unbuf_err_code_cg_wrap[]'. This is because both the covergroup instances are having same description and are defined in the same scope with the same name.
xmsim: *E,COVITS: Covergroup instance unbuf_err_code_cg (/nightly/current_run/scratch/master/otp_ctrl-sim-xcelium/cover_reg_top/fusesoc-work/src/lowrisc_darjeeling_dv_otp_ctrl_env_0.1/otp_ctrl_env_cov.sv:12) with 'unbuf_err_code_cg_wrap[]' as the instance name will not be saved to the database and its coverage will be merged with another covergroup instance unbuf_err_code_cg (/nightly/current_run/scratch/master/otp_ctrl-sim-xcelium/cover_reg_top/fusesoc-work/src/lowrisc_darjeeling_dv_otp_ctrl_env_0.1/otp_ctrl_env_cov.sv:12) with the same instance name 'unbuf_err_code_cg_wrap[]'. This is because both the covergroup instances are having same description and are defined in the same scope with the same name.
xmsim: *E,COVITS: Covergroup instance unbuf_err_code_cg (/nightly/current_run/scratch/master/otp_ctrl-sim-xcelium/cover_reg_top/fusesoc-work/src/lowrisc_darjeeling_dv_otp_ctrl_env_0.1/otp_ctrl_env_cov.sv:12) with 'unbuf_err_code_cg_wrap[]' as the instance name will not be saved to the database and its coverage will be merged with another covergroup instance unbuf_err_code_cg (/nightly/current_run/scratch/master/otp_ctrl-sim-xcelium/cover_reg_top/fusesoc-work/src/lowrisc_darjeeling_dv_otp_ctrl_env_0.1/otp_ctrl_env_cov.sv:12) with the same instance name 'unbuf_err_code_cg_wrap[]'. This is because both the covergroup instances are having same description and are defined in the same scope with the same name.
xmsim: *W,CGPIZE: Instance coverage for covergroup instance "lc_esc_en_condition_cg_inst" will not be dumped to database as per_instance option value is set to 0:/nightly/current_run/scratch/master/otp_ctrl-sim-xcelium/cover_reg_top/fusesoc-work/src/lowrisc_darjeeling_dv_otp_ctrl_cov_0/otp_ctrl_cov_if.sv, 71.
xmsim: *W,CGPIZE: Instance coverage for covergroup instance "sram_0_req_condition_cg_inst" will not be dumped to database as per_instance option value is set to 0:/nightly/current_run/scratch/master/otp_ctrl-sim-xcelium/cover_reg_top/fusesoc-work/src/lowrisc_darjeeling_dv_otp_ctrl_cov_0/otp_ctrl_cov_if.sv, 72.
|
|
| otp_ctrl_csr_rw | 37327256688722508889477028812339308779278511920276464346383535267080835664488 | 189 |
xmsim: *E,COVITS: Covergroup instance unbuf_err_code_cg (/nightly/current_run/scratch/master/otp_ctrl-sim-xcelium/cover_reg_top/fusesoc-work/src/lowrisc_darjeeling_dv_otp_ctrl_env_0.1/otp_ctrl_env_cov.sv:12) with 'unbuf_err_code_cg_wrap[]' as the instance name will not be saved to the database and its coverage will be merged with another covergroup instance unbuf_err_code_cg (/nightly/current_run/scratch/master/otp_ctrl-sim-xcelium/cover_reg_top/fusesoc-work/src/lowrisc_darjeeling_dv_otp_ctrl_env_0.1/otp_ctrl_env_cov.sv:12) with the same instance name 'unbuf_err_code_cg_wrap[]'. This is because both the covergroup instances are having same description and are defined in the same scope with the same name.
xmsim: *E,COVITS: Covergroup instance unbuf_err_code_cg (/nightly/current_run/scratch/master/otp_ctrl-sim-xcelium/cover_reg_top/fusesoc-work/src/lowrisc_darjeeling_dv_otp_ctrl_env_0.1/otp_ctrl_env_cov.sv:12) with 'unbuf_err_code_cg_wrap[]' as the instance name will not be saved to the database and its coverage will be merged with another covergroup instance unbuf_err_code_cg (/nightly/current_run/scratch/master/otp_ctrl-sim-xcelium/cover_reg_top/fusesoc-work/src/lowrisc_darjeeling_dv_otp_ctrl_env_0.1/otp_ctrl_env_cov.sv:12) with the same instance name 'unbuf_err_code_cg_wrap[]'. This is because both the covergroup instances are having same description and are defined in the same scope with the same name.
xmsim: *E,COVITS: Covergroup instance unbuf_err_code_cg (/nightly/current_run/scratch/master/otp_ctrl-sim-xcelium/cover_reg_top/fusesoc-work/src/lowrisc_darjeeling_dv_otp_ctrl_env_0.1/otp_ctrl_env_cov.sv:12) with 'unbuf_err_code_cg_wrap[]' as the instance name will not be saved to the database and its coverage will be merged with another covergroup instance unbuf_err_code_cg (/nightly/current_run/scratch/master/otp_ctrl-sim-xcelium/cover_reg_top/fusesoc-work/src/lowrisc_darjeeling_dv_otp_ctrl_env_0.1/otp_ctrl_env_cov.sv:12) with the same instance name 'unbuf_err_code_cg_wrap[]'. This is because both the covergroup instances are having same description and are defined in the same scope with the same name.
xmsim: *W,CGPIZE: Instance coverage for covergroup instance "lc_esc_en_condition_cg_inst" will not be dumped to database as per_instance option value is set to 0:/nightly/current_run/scratch/master/otp_ctrl-sim-xcelium/cover_reg_top/fusesoc-work/src/lowrisc_darjeeling_dv_otp_ctrl_cov_0/otp_ctrl_cov_if.sv, 71.
xmsim: *W,CGPIZE: Instance coverage for covergroup instance "sram_0_req_condition_cg_inst" will not be dumped to database as per_instance option value is set to 0:/nightly/current_run/scratch/master/otp_ctrl-sim-xcelium/cover_reg_top/fusesoc-work/src/lowrisc_darjeeling_dv_otp_ctrl_cov_0/otp_ctrl_cov_if.sv, 72.
|
|
| otp_ctrl_csr_bit_bash | 18445995967829870021449077696856966902068829786309697419168483685571708897881 | 190 |
xmsim: *E,COVITS: Covergroup instance unbuf_err_code_cg (/nightly/current_run/scratch/master/otp_ctrl-sim-xcelium/cover_reg_top/fusesoc-work/src/lowrisc_darjeeling_dv_otp_ctrl_env_0.1/otp_ctrl_env_cov.sv:12) with 'unbuf_err_code_cg_wrap[]' as the instance name will not be saved to the database and its coverage will be merged with another covergroup instance unbuf_err_code_cg (/nightly/current_run/scratch/master/otp_ctrl-sim-xcelium/cover_reg_top/fusesoc-work/src/lowrisc_darjeeling_dv_otp_ctrl_env_0.1/otp_ctrl_env_cov.sv:12) with the same instance name 'unbuf_err_code_cg_wrap[]'. This is because both the covergroup instances are having same description and are defined in the same scope with the same name.
xmsim: *E,COVITS: Covergroup instance unbuf_err_code_cg (/nightly/current_run/scratch/master/otp_ctrl-sim-xcelium/cover_reg_top/fusesoc-work/src/lowrisc_darjeeling_dv_otp_ctrl_env_0.1/otp_ctrl_env_cov.sv:12) with 'unbuf_err_code_cg_wrap[]' as the instance name will not be saved to the database and its coverage will be merged with another covergroup instance unbuf_err_code_cg (/nightly/current_run/scratch/master/otp_ctrl-sim-xcelium/cover_reg_top/fusesoc-work/src/lowrisc_darjeeling_dv_otp_ctrl_env_0.1/otp_ctrl_env_cov.sv:12) with the same instance name 'unbuf_err_code_cg_wrap[]'. This is because both the covergroup instances are having same description and are defined in the same scope with the same name.
xmsim: *E,COVITS: Covergroup instance unbuf_err_code_cg (/nightly/current_run/scratch/master/otp_ctrl-sim-xcelium/cover_reg_top/fusesoc-work/src/lowrisc_darjeeling_dv_otp_ctrl_env_0.1/otp_ctrl_env_cov.sv:12) with 'unbuf_err_code_cg_wrap[]' as the instance name will not be saved to the database and its coverage will be merged with another covergroup instance unbuf_err_code_cg (/nightly/current_run/scratch/master/otp_ctrl-sim-xcelium/cover_reg_top/fusesoc-work/src/lowrisc_darjeeling_dv_otp_ctrl_env_0.1/otp_ctrl_env_cov.sv:12) with the same instance name 'unbuf_err_code_cg_wrap[]'. This is because both the covergroup instances are having same description and are defined in the same scope with the same name.
xmsim: *W,CGPIZE: Instance coverage for covergroup instance "lc_esc_en_condition_cg_inst" will not be dumped to database as per_instance option value is set to 0:/nightly/current_run/scratch/master/otp_ctrl-sim-xcelium/cover_reg_top/fusesoc-work/src/lowrisc_darjeeling_dv_otp_ctrl_cov_0/otp_ctrl_cov_if.sv, 71.
xmsim: *W,CGPIZE: Instance coverage for covergroup instance "sram_0_req_condition_cg_inst" will not be dumped to database as per_instance option value is set to 0:/nightly/current_run/scratch/master/otp_ctrl-sim-xcelium/cover_reg_top/fusesoc-work/src/lowrisc_darjeeling_dv_otp_ctrl_cov_0/otp_ctrl_cov_if.sv, 72.
|
|
| otp_ctrl_csr_aliasing | 98258645710167396655977906787169694423321858806257101601356583911394249761188 | 190 |
xmsim: *E,COVITS: Covergroup instance unbuf_err_code_cg (/nightly/current_run/scratch/master/otp_ctrl-sim-xcelium/cover_reg_top/fusesoc-work/src/lowrisc_darjeeling_dv_otp_ctrl_env_0.1/otp_ctrl_env_cov.sv:12) with 'unbuf_err_code_cg_wrap[]' as the instance name will not be saved to the database and its coverage will be merged with another covergroup instance unbuf_err_code_cg (/nightly/current_run/scratch/master/otp_ctrl-sim-xcelium/cover_reg_top/fusesoc-work/src/lowrisc_darjeeling_dv_otp_ctrl_env_0.1/otp_ctrl_env_cov.sv:12) with the same instance name 'unbuf_err_code_cg_wrap[]'. This is because both the covergroup instances are having same description and are defined in the same scope with the same name.
xmsim: *E,COVITS: Covergroup instance unbuf_err_code_cg (/nightly/current_run/scratch/master/otp_ctrl-sim-xcelium/cover_reg_top/fusesoc-work/src/lowrisc_darjeeling_dv_otp_ctrl_env_0.1/otp_ctrl_env_cov.sv:12) with 'unbuf_err_code_cg_wrap[]' as the instance name will not be saved to the database and its coverage will be merged with another covergroup instance unbuf_err_code_cg (/nightly/current_run/scratch/master/otp_ctrl-sim-xcelium/cover_reg_top/fusesoc-work/src/lowrisc_darjeeling_dv_otp_ctrl_env_0.1/otp_ctrl_env_cov.sv:12) with the same instance name 'unbuf_err_code_cg_wrap[]'. This is because both the covergroup instances are having same description and are defined in the same scope with the same name.
xmsim: *E,COVITS: Covergroup instance unbuf_err_code_cg (/nightly/current_run/scratch/master/otp_ctrl-sim-xcelium/cover_reg_top/fusesoc-work/src/lowrisc_darjeeling_dv_otp_ctrl_env_0.1/otp_ctrl_env_cov.sv:12) with 'unbuf_err_code_cg_wrap[]' as the instance name will not be saved to the database and its coverage will be merged with another covergroup instance unbuf_err_code_cg (/nightly/current_run/scratch/master/otp_ctrl-sim-xcelium/cover_reg_top/fusesoc-work/src/lowrisc_darjeeling_dv_otp_ctrl_env_0.1/otp_ctrl_env_cov.sv:12) with the same instance name 'unbuf_err_code_cg_wrap[]'. This is because both the covergroup instances are having same description and are defined in the same scope with the same name.
xmsim: *W,CGPIZE: Instance coverage for covergroup instance "lc_esc_en_condition_cg_inst" will not be dumped to database as per_instance option value is set to 0:/nightly/current_run/scratch/master/otp_ctrl-sim-xcelium/cover_reg_top/fusesoc-work/src/lowrisc_darjeeling_dv_otp_ctrl_cov_0/otp_ctrl_cov_if.sv, 71.
xmsim: *W,CGPIZE: Instance coverage for covergroup instance "sram_0_req_condition_cg_inst" will not be dumped to database as per_instance option value is set to 0:/nightly/current_run/scratch/master/otp_ctrl-sim-xcelium/cover_reg_top/fusesoc-work/src/lowrisc_darjeeling_dv_otp_ctrl_cov_0/otp_ctrl_cov_if.sv, 72.
|
|
| otp_ctrl_same_csr_outstanding | 114950385208902841099181503637129876082343813134732358202743102049008114406823 | 191 |
xmsim: *E,COVITS: Covergroup instance unbuf_err_code_cg (/nightly/current_run/scratch/master/otp_ctrl-sim-xcelium/cover_reg_top/fusesoc-work/src/lowrisc_darjeeling_dv_otp_ctrl_env_0.1/otp_ctrl_env_cov.sv:12) with 'unbuf_err_code_cg_wrap[]' as the instance name will not be saved to the database and its coverage will be merged with another covergroup instance unbuf_err_code_cg (/nightly/current_run/scratch/master/otp_ctrl-sim-xcelium/cover_reg_top/fusesoc-work/src/lowrisc_darjeeling_dv_otp_ctrl_env_0.1/otp_ctrl_env_cov.sv:12) with the same instance name 'unbuf_err_code_cg_wrap[]'. This is because both the covergroup instances are having same description and are defined in the same scope with the same name.
xmsim: *E,COVITS: Covergroup instance unbuf_err_code_cg (/nightly/current_run/scratch/master/otp_ctrl-sim-xcelium/cover_reg_top/fusesoc-work/src/lowrisc_darjeeling_dv_otp_ctrl_env_0.1/otp_ctrl_env_cov.sv:12) with 'unbuf_err_code_cg_wrap[]' as the instance name will not be saved to the database and its coverage will be merged with another covergroup instance unbuf_err_code_cg (/nightly/current_run/scratch/master/otp_ctrl-sim-xcelium/cover_reg_top/fusesoc-work/src/lowrisc_darjeeling_dv_otp_ctrl_env_0.1/otp_ctrl_env_cov.sv:12) with the same instance name 'unbuf_err_code_cg_wrap[]'. This is because both the covergroup instances are having same description and are defined in the same scope with the same name.
xmsim: *E,COVITS: Covergroup instance unbuf_err_code_cg (/nightly/current_run/scratch/master/otp_ctrl-sim-xcelium/cover_reg_top/fusesoc-work/src/lowrisc_darjeeling_dv_otp_ctrl_env_0.1/otp_ctrl_env_cov.sv:12) with 'unbuf_err_code_cg_wrap[]' as the instance name will not be saved to the database and its coverage will be merged with another covergroup instance unbuf_err_code_cg (/nightly/current_run/scratch/master/otp_ctrl-sim-xcelium/cover_reg_top/fusesoc-work/src/lowrisc_darjeeling_dv_otp_ctrl_env_0.1/otp_ctrl_env_cov.sv:12) with the same instance name 'unbuf_err_code_cg_wrap[]'. This is because both the covergroup instances are having same description and are defined in the same scope with the same name.
xmsim: *W,CGPIZE: Instance coverage for covergroup instance "lc_esc_en_condition_cg_inst" will not be dumped to database as per_instance option value is set to 0:/nightly/current_run/scratch/master/otp_ctrl-sim-xcelium/cover_reg_top/fusesoc-work/src/lowrisc_darjeeling_dv_otp_ctrl_cov_0/otp_ctrl_cov_if.sv, 71.
xmsim: *W,CGPIZE: Instance coverage for covergroup instance "sram_0_req_condition_cg_inst" will not be dumped to database as per_instance option value is set to 0:/nightly/current_run/scratch/master/otp_ctrl-sim-xcelium/cover_reg_top/fusesoc-work/src/lowrisc_darjeeling_dv_otp_ctrl_cov_0/otp_ctrl_cov_if.sv, 72.
|
|
| otp_ctrl_csr_mem_rw_with_rand_reset | 36188171747975163670130794572962001201058975834246202943233257588076427051498 | 194 |
xmsim: *E,COVITS: Covergroup instance unbuf_err_code_cg (/nightly/current_run/scratch/master/otp_ctrl-sim-xcelium/cover_reg_top/fusesoc-work/src/lowrisc_darjeeling_dv_otp_ctrl_env_0.1/otp_ctrl_env_cov.sv:12) with 'unbuf_err_code_cg_wrap[]' as the instance name will not be saved to the database and its coverage will be merged with another covergroup instance unbuf_err_code_cg (/nightly/current_run/scratch/master/otp_ctrl-sim-xcelium/cover_reg_top/fusesoc-work/src/lowrisc_darjeeling_dv_otp_ctrl_env_0.1/otp_ctrl_env_cov.sv:12) with the same instance name 'unbuf_err_code_cg_wrap[]'. This is because both the covergroup instances are having same description and are defined in the same scope with the same name.
xmsim: *E,COVITS: Covergroup instance unbuf_err_code_cg (/nightly/current_run/scratch/master/otp_ctrl-sim-xcelium/cover_reg_top/fusesoc-work/src/lowrisc_darjeeling_dv_otp_ctrl_env_0.1/otp_ctrl_env_cov.sv:12) with 'unbuf_err_code_cg_wrap[]' as the instance name will not be saved to the database and its coverage will be merged with another covergroup instance unbuf_err_code_cg (/nightly/current_run/scratch/master/otp_ctrl-sim-xcelium/cover_reg_top/fusesoc-work/src/lowrisc_darjeeling_dv_otp_ctrl_env_0.1/otp_ctrl_env_cov.sv:12) with the same instance name 'unbuf_err_code_cg_wrap[]'. This is because both the covergroup instances are having same description and are defined in the same scope with the same name.
xmsim: *E,COVITS: Covergroup instance unbuf_err_code_cg (/nightly/current_run/scratch/master/otp_ctrl-sim-xcelium/cover_reg_top/fusesoc-work/src/lowrisc_darjeeling_dv_otp_ctrl_env_0.1/otp_ctrl_env_cov.sv:12) with 'unbuf_err_code_cg_wrap[]' as the instance name will not be saved to the database and its coverage will be merged with another covergroup instance unbuf_err_code_cg (/nightly/current_run/scratch/master/otp_ctrl-sim-xcelium/cover_reg_top/fusesoc-work/src/lowrisc_darjeeling_dv_otp_ctrl_env_0.1/otp_ctrl_env_cov.sv:12) with the same instance name 'unbuf_err_code_cg_wrap[]'. This is because both the covergroup instances are having same description and are defined in the same scope with the same name.
xmsim: *W,CGPIZE: Instance coverage for covergroup instance "lc_esc_en_condition_cg_inst" will not be dumped to database as per_instance option value is set to 0:/nightly/current_run/scratch/master/otp_ctrl-sim-xcelium/cover_reg_top/fusesoc-work/src/lowrisc_darjeeling_dv_otp_ctrl_cov_0/otp_ctrl_cov_if.sv, 71.
xmsim: *W,CGPIZE: Instance coverage for covergroup instance "sram_0_req_condition_cg_inst" will not be dumped to database as per_instance option value is set to 0:/nightly/current_run/scratch/master/otp_ctrl-sim-xcelium/cover_reg_top/fusesoc-work/src/lowrisc_darjeeling_dv_otp_ctrl_cov_0/otp_ctrl_cov_if.sv, 72.
|
|
| xmsim: *E,COVITS: Covergroup instance unbuf_err_code_cg (/nightly/current_run/scratch/master/otp_ctrl-sim-xcelium/default/fusesoc-work/src/lowrisc_darjeeling_dv_otp_ctrl_env_*/otp_ctrl_env_cov.sv:12) with 'unbuf_err_code_cg_wrap[]' as the instance name will not be saved to the database and its coverage will be merged with another covergroup instance unbuf_err_code_cg (/nightly/current_run/scratch/master/otp_ctrl-sim-xcelium/default/fusesoc-work/src/lowrisc_darjeeling_dv_otp_ctrl_env_*/otp_ctrl_env_cov.sv:12) with the same instance name 'unbuf_err_code_cg_wrap[]'. This is because both the covergroup instances are having same description and are defined in the same scope with the same name. | ||||
| otp_ctrl_wake_up | 83214826651193756735688851154464501710818414284384799356183095233720396470620 | 187 |
xmsim: *E,COVITS: Covergroup instance unbuf_err_code_cg (/nightly/current_run/scratch/master/otp_ctrl-sim-xcelium/default/fusesoc-work/src/lowrisc_darjeeling_dv_otp_ctrl_env_0.1/otp_ctrl_env_cov.sv:12) with 'unbuf_err_code_cg_wrap[]' as the instance name will not be saved to the database and its coverage will be merged with another covergroup instance unbuf_err_code_cg (/nightly/current_run/scratch/master/otp_ctrl-sim-xcelium/default/fusesoc-work/src/lowrisc_darjeeling_dv_otp_ctrl_env_0.1/otp_ctrl_env_cov.sv:12) with the same instance name 'unbuf_err_code_cg_wrap[]'. This is because both the covergroup instances are having same description and are defined in the same scope with the same name.
xmsim: *E,COVITS: Covergroup instance unbuf_err_code_cg (/nightly/current_run/scratch/master/otp_ctrl-sim-xcelium/default/fusesoc-work/src/lowrisc_darjeeling_dv_otp_ctrl_env_0.1/otp_ctrl_env_cov.sv:12) with 'unbuf_err_code_cg_wrap[]' as the instance name will not be saved to the database and its coverage will be merged with another covergroup instance unbuf_err_code_cg (/nightly/current_run/scratch/master/otp_ctrl-sim-xcelium/default/fusesoc-work/src/lowrisc_darjeeling_dv_otp_ctrl_env_0.1/otp_ctrl_env_cov.sv:12) with the same instance name 'unbuf_err_code_cg_wrap[]'. This is because both the covergroup instances are having same description and are defined in the same scope with the same name.
xmsim: *E,COVITS: Covergroup instance unbuf_err_code_cg (/nightly/current_run/scratch/master/otp_ctrl-sim-xcelium/default/fusesoc-work/src/lowrisc_darjeeling_dv_otp_ctrl_env_0.1/otp_ctrl_env_cov.sv:12) with 'unbuf_err_code_cg_wrap[]' as the instance name will not be saved to the database and its coverage will be merged with another covergroup instance unbuf_err_code_cg (/nightly/current_run/scratch/master/otp_ctrl-sim-xcelium/default/fusesoc-work/src/lowrisc_darjeeling_dv_otp_ctrl_env_0.1/otp_ctrl_env_cov.sv:12) with the same instance name 'unbuf_err_code_cg_wrap[]'. This is because both the covergroup instances are having same description and are defined in the same scope with the same name.
xmsim: *W,CGPIZE: Instance coverage for covergroup instance "lc_esc_en_condition_cg_inst" will not be dumped to database as per_instance option value is set to 0:/nightly/current_run/scratch/master/otp_ctrl-sim-xcelium/default/fusesoc-work/src/lowrisc_darjeeling_dv_otp_ctrl_cov_0/otp_ctrl_cov_if.sv, 71.
xmsim: *W,CGPIZE: Instance coverage for covergroup instance "sram_0_req_condition_cg_inst" will not be dumped to database as per_instance option value is set to 0:/nightly/current_run/scratch/master/otp_ctrl-sim-xcelium/default/fusesoc-work/src/lowrisc_darjeeling_dv_otp_ctrl_cov_0/otp_ctrl_cov_if.sv, 72.
|
|
| otp_ctrl_background_chks | 37621898014288331798253616071945249943389368903590330412773344816866048590379 | 4360 |
xmsim: *E,COVITS: Covergroup instance unbuf_err_code_cg (/nightly/current_run/scratch/master/otp_ctrl-sim-xcelium/default/fusesoc-work/src/lowrisc_darjeeling_dv_otp_ctrl_env_0.1/otp_ctrl_env_cov.sv:12) with 'unbuf_err_code_cg_wrap[]' as the instance name will not be saved to the database and its coverage will be merged with another covergroup instance unbuf_err_code_cg (/nightly/current_run/scratch/master/otp_ctrl-sim-xcelium/default/fusesoc-work/src/lowrisc_darjeeling_dv_otp_ctrl_env_0.1/otp_ctrl_env_cov.sv:12) with the same instance name 'unbuf_err_code_cg_wrap[]'. This is because both the covergroup instances are having same description and are defined in the same scope with the same name.
xmsim: *E,COVITS: Covergroup instance unbuf_err_code_cg (/nightly/current_run/scratch/master/otp_ctrl-sim-xcelium/default/fusesoc-work/src/lowrisc_darjeeling_dv_otp_ctrl_env_0.1/otp_ctrl_env_cov.sv:12) with 'unbuf_err_code_cg_wrap[]' as the instance name will not be saved to the database and its coverage will be merged with another covergroup instance unbuf_err_code_cg (/nightly/current_run/scratch/master/otp_ctrl-sim-xcelium/default/fusesoc-work/src/lowrisc_darjeeling_dv_otp_ctrl_env_0.1/otp_ctrl_env_cov.sv:12) with the same instance name 'unbuf_err_code_cg_wrap[]'. This is because both the covergroup instances are having same description and are defined in the same scope with the same name.
xmsim: *E,COVITS: Covergroup instance unbuf_err_code_cg (/nightly/current_run/scratch/master/otp_ctrl-sim-xcelium/default/fusesoc-work/src/lowrisc_darjeeling_dv_otp_ctrl_env_0.1/otp_ctrl_env_cov.sv:12) with 'unbuf_err_code_cg_wrap[]' as the instance name will not be saved to the database and its coverage will be merged with another covergroup instance unbuf_err_code_cg (/nightly/current_run/scratch/master/otp_ctrl-sim-xcelium/default/fusesoc-work/src/lowrisc_darjeeling_dv_otp_ctrl_env_0.1/otp_ctrl_env_cov.sv:12) with the same instance name 'unbuf_err_code_cg_wrap[]'. This is because both the covergroup instances are having same description and are defined in the same scope with the same name.
xmsim: *W,CGPIZE: Instance coverage for covergroup instance "lc_esc_en_condition_cg_inst" will not be dumped to database as per_instance option value is set to 0:/nightly/current_run/scratch/master/otp_ctrl-sim-xcelium/default/fusesoc-work/src/lowrisc_darjeeling_dv_otp_ctrl_cov_0/otp_ctrl_cov_if.sv, 71.
xmsim: *W,CGPIZE: Instance coverage for covergroup instance "sram_0_req_condition_cg_inst" will not be dumped to database as per_instance option value is set to 0:/nightly/current_run/scratch/master/otp_ctrl-sim-xcelium/default/fusesoc-work/src/lowrisc_darjeeling_dv_otp_ctrl_cov_0/otp_ctrl_cov_if.sv, 72.
|
|
| otp_ctrl_test_access | 100917424222472886496652553729562627980283254415374831039343548943232203292835 | 5461 |
xmsim: *E,COVITS: Covergroup instance unbuf_err_code_cg (/nightly/current_run/scratch/master/otp_ctrl-sim-xcelium/default/fusesoc-work/src/lowrisc_darjeeling_dv_otp_ctrl_env_0.1/otp_ctrl_env_cov.sv:12) with 'unbuf_err_code_cg_wrap[]' as the instance name will not be saved to the database and its coverage will be merged with another covergroup instance unbuf_err_code_cg (/nightly/current_run/scratch/master/otp_ctrl-sim-xcelium/default/fusesoc-work/src/lowrisc_darjeeling_dv_otp_ctrl_env_0.1/otp_ctrl_env_cov.sv:12) with the same instance name 'unbuf_err_code_cg_wrap[]'. This is because both the covergroup instances are having same description and are defined in the same scope with the same name.
xmsim: *E,COVITS: Covergroup instance unbuf_err_code_cg (/nightly/current_run/scratch/master/otp_ctrl-sim-xcelium/default/fusesoc-work/src/lowrisc_darjeeling_dv_otp_ctrl_env_0.1/otp_ctrl_env_cov.sv:12) with 'unbuf_err_code_cg_wrap[]' as the instance name will not be saved to the database and its coverage will be merged with another covergroup instance unbuf_err_code_cg (/nightly/current_run/scratch/master/otp_ctrl-sim-xcelium/default/fusesoc-work/src/lowrisc_darjeeling_dv_otp_ctrl_env_0.1/otp_ctrl_env_cov.sv:12) with the same instance name 'unbuf_err_code_cg_wrap[]'. This is because both the covergroup instances are having same description and are defined in the same scope with the same name.
xmsim: *E,COVITS: Covergroup instance unbuf_err_code_cg (/nightly/current_run/scratch/master/otp_ctrl-sim-xcelium/default/fusesoc-work/src/lowrisc_darjeeling_dv_otp_ctrl_env_0.1/otp_ctrl_env_cov.sv:12) with 'unbuf_err_code_cg_wrap[]' as the instance name will not be saved to the database and its coverage will be merged with another covergroup instance unbuf_err_code_cg (/nightly/current_run/scratch/master/otp_ctrl-sim-xcelium/default/fusesoc-work/src/lowrisc_darjeeling_dv_otp_ctrl_env_0.1/otp_ctrl_env_cov.sv:12) with the same instance name 'unbuf_err_code_cg_wrap[]'. This is because both the covergroup instances are having same description and are defined in the same scope with the same name.
xmsim: *W,CGPIZE: Instance coverage for covergroup instance "lc_esc_en_condition_cg_inst" will not be dumped to database as per_instance option value is set to 0:/nightly/current_run/scratch/master/otp_ctrl-sim-xcelium/default/fusesoc-work/src/lowrisc_darjeeling_dv_otp_ctrl_cov_0/otp_ctrl_cov_if.sv, 71.
xmsim: *W,CGPIZE: Instance coverage for covergroup instance "sram_0_req_condition_cg_inst" will not be dumped to database as per_instance option value is set to 0:/nightly/current_run/scratch/master/otp_ctrl-sim-xcelium/default/fusesoc-work/src/lowrisc_darjeeling_dv_otp_ctrl_cov_0/otp_ctrl_cov_if.sv, 72.
|
|
| otp_ctrl_alert_test | 115513128433261317220160295361583962360128943510087328151006360361162110665606 | 189 |
xmsim: *E,COVITS: Covergroup instance unbuf_err_code_cg (/nightly/current_run/scratch/master/otp_ctrl-sim-xcelium/default/fusesoc-work/src/lowrisc_darjeeling_dv_otp_ctrl_env_0.1/otp_ctrl_env_cov.sv:12) with 'unbuf_err_code_cg_wrap[]' as the instance name will not be saved to the database and its coverage will be merged with another covergroup instance unbuf_err_code_cg (/nightly/current_run/scratch/master/otp_ctrl-sim-xcelium/default/fusesoc-work/src/lowrisc_darjeeling_dv_otp_ctrl_env_0.1/otp_ctrl_env_cov.sv:12) with the same instance name 'unbuf_err_code_cg_wrap[]'. This is because both the covergroup instances are having same description and are defined in the same scope with the same name.
xmsim: *E,COVITS: Covergroup instance unbuf_err_code_cg (/nightly/current_run/scratch/master/otp_ctrl-sim-xcelium/default/fusesoc-work/src/lowrisc_darjeeling_dv_otp_ctrl_env_0.1/otp_ctrl_env_cov.sv:12) with 'unbuf_err_code_cg_wrap[]' as the instance name will not be saved to the database and its coverage will be merged with another covergroup instance unbuf_err_code_cg (/nightly/current_run/scratch/master/otp_ctrl-sim-xcelium/default/fusesoc-work/src/lowrisc_darjeeling_dv_otp_ctrl_env_0.1/otp_ctrl_env_cov.sv:12) with the same instance name 'unbuf_err_code_cg_wrap[]'. This is because both the covergroup instances are having same description and are defined in the same scope with the same name.
xmsim: *E,COVITS: Covergroup instance unbuf_err_code_cg (/nightly/current_run/scratch/master/otp_ctrl-sim-xcelium/default/fusesoc-work/src/lowrisc_darjeeling_dv_otp_ctrl_env_0.1/otp_ctrl_env_cov.sv:12) with 'unbuf_err_code_cg_wrap[]' as the instance name will not be saved to the database and its coverage will be merged with another covergroup instance unbuf_err_code_cg (/nightly/current_run/scratch/master/otp_ctrl-sim-xcelium/default/fusesoc-work/src/lowrisc_darjeeling_dv_otp_ctrl_env_0.1/otp_ctrl_env_cov.sv:12) with the same instance name 'unbuf_err_code_cg_wrap[]'. This is because both the covergroup instances are having same description and are defined in the same scope with the same name.
xmsim: *W,CGPIZE: Instance coverage for covergroup instance "lc_esc_en_condition_cg_inst" will not be dumped to database as per_instance option value is set to 0:/nightly/current_run/scratch/master/otp_ctrl-sim-xcelium/default/fusesoc-work/src/lowrisc_darjeeling_dv_otp_ctrl_cov_0/otp_ctrl_cov_if.sv, 71.
xmsim: *W,CGPIZE: Instance coverage for covergroup instance "sram_0_req_condition_cg_inst" will not be dumped to database as per_instance option value is set to 0:/nightly/current_run/scratch/master/otp_ctrl-sim-xcelium/default/fusesoc-work/src/lowrisc_darjeeling_dv_otp_ctrl_cov_0/otp_ctrl_cov_if.sv, 72.
|
|
| UVM_ERROR (csr_utils_pkg.sv:458) [csr_utils_pkg::csr_rd_check.isolation_fork.unmblk1] Check failed obs == exp (* [*] vs * [*]) Regname: otp_ctrl_core_reg_block.status.dai_idle reset value: * | ||||
| otp_ctrl_smoke | 32732492485677353521322000678522850102597773472494545228227642949661705554792 | 665 |
UVM_ERROR @ 641178969 ps: (csr_utils_pkg.sv:458) [csr_utils_pkg::csr_rd_check.isolation_fork.unmblk1] Check failed obs == exp (1 [0x1] vs 0 [0x0]) Regname: otp_ctrl_core_reg_block.status.dai_idle reset value: 0x0
UVM_INFO @ 641178969 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| otp_ctrl_partition_walk | 60863101620110988159546642259043869154848747227778858233868002620268038789220 | 165516 |
UVM_ERROR @ 2403051414 ps: (csr_utils_pkg.sv:458) [csr_utils_pkg::csr_rd_check.isolation_fork.unmblk1] Check failed obs == exp (1 [0x1] vs 0 [0x0]) Regname: otp_ctrl_core_reg_block.status.dai_idle reset value: 0x0
UVM_INFO @ 2403051414 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| otp_ctrl_init_fail | 96407442519726987890825143999663933957693262574344747440531369848556781750360 | 1850 |
UVM_ERROR @ 113418852 ps: (csr_utils_pkg.sv:458) [csr_utils_pkg::csr_rd_check.isolation_fork.unmblk1] Check failed obs == exp (1 [0x1] vs 0 [0x0]) Regname: otp_ctrl_core_reg_block.status.dai_idle reset value: 0x0
UVM_INFO @ 113418852 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| otp_ctrl_regwen | 53517028129198765245807336881647291766084905411858008283760842194825978692295 | 5057 |
UVM_ERROR @ 791822489 ps: (csr_utils_pkg.sv:458) [csr_utils_pkg::csr_rd_check.isolation_fork.unmblk1] Check failed obs == exp (1 [0x1] vs 0 [0x0]) Regname: otp_ctrl_core_reg_block.status.dai_idle reset value: 0x0
UVM_INFO @ 791822489 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| UVM_ERROR (otp_ctrl_base_vseq.sv:215) [otp_ctrl_low_freq_read_vseq] Check failed rdata* == exp_data* (* [*] vs * [*]) dai addr *ed* rdata* readout mismatch | ||||
| otp_ctrl_low_freq_read | 39220226099467529576632965861348156967381377758835573969152015849245118616028 | 110 |
UVM_ERROR @ 59183026523 ps: (otp_ctrl_base_vseq.sv:215) [uvm_test_top.env.virtual_sequencer.otp_ctrl_low_freq_read_vseq] Check failed rdata0 == exp_data0 (16080 [0x3ed0] vs 3032406676 [0xb4beda94]) dai addr 3ed0 rdata0 readout mismatch
UVM_INFO @ 59183026523 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| UVM_ERROR (otp_ctrl_scoreboard.sv:959) [scoreboard] Check failed (csr.get_mirrored_value() | status_mask) == (item.d_data | status_mask) (* [*] vs * [*]) reg name: status, compare_mask * | ||||
| otp_ctrl_parallel_lc_req | 77050530876315914976925410221461126652140843036254708521946453239543112914231 | 5088 |
UVM_ERROR @ 377031983 ps: (otp_ctrl_scoreboard.sv:959) [uvm_test_top.env.scoreboard] Check failed (csr.get_mirrored_value() | status_mask) == (item.d_data | status_mask) (263 [0x107] vs 261 [0x105]) reg name: status, compare_mask 4
UVM_INFO @ 377031983 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| UVM_ERROR (otp_ctrl_scoreboard.sv:1321) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) reg name: otp_ctrl_core_reg_block.err_code_* | ||||
| otp_ctrl_parallel_lc_esc | 6626047457849966021896746267694569572989440921370252738359212786355065227132 | 857 |
UVM_ERROR @ 142344658 ps: (otp_ctrl_scoreboard.sv:1321) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (4 [0x4] vs 5 [0x5]) reg name: otp_ctrl_core_reg_block.err_code_22
UVM_INFO @ 142344658 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| otp_ctrl_dai_lock | 70280213116013315939628159740853688966612415306779320140104493311343593683742 | 4518 |
UVM_ERROR @ 5279185111 ps: (otp_ctrl_scoreboard.sv:1321) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (4 [0x4] vs 5 [0x5]) reg name: otp_ctrl_core_reg_block.err_code_22
UVM_INFO @ 5279185111 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| otp_ctrl_parallel_key_req | 16830941565106274158439940169226471866056524635612867227091108773346969199665 | 6176 |
UVM_ERROR @ 354921782 ps: (otp_ctrl_scoreboard.sv:1321) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (4 [0x4] vs 5 [0x5]) reg name: otp_ctrl_core_reg_block.err_code_22
UVM_INFO @ 354921782 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
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| otp_ctrl_stress_all | 108667013709248555718416474319807798245437439153394752808519916589226973182418 | 2277 |
UVM_ERROR @ 268068794 ps: (otp_ctrl_scoreboard.sv:1321) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (4 [0x4] vs 5 [0x5]) reg name: otp_ctrl_core_reg_block.err_code_22
UVM_INFO @ 268068794 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
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| UVM_FATAL (csr_utils_pkg.sv:618) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout otp_ctrl_core_reg_block.status.dai_idle (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=95) | ||||
| otp_ctrl_dai_errs | 93259713764916358228792628151971475376964346271265378397969644074581807779313 | 1007544 |
UVM_FATAL @ 20262914480 ps: (csr_utils_pkg.sv:618) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout otp_ctrl_core_reg_block.status.dai_idle (addr=0x7eb98010, Comparison=CompareOpEq, exp_data=0x1, call_count=95)
UVM_INFO @ 20262914480 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
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| UVM_ERROR (otp_ctrl_scoreboard.sv:1321) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) reg name: otp_ctrl_core_reg_block.direct_access_rdata_* | ||||
| otp_ctrl_check_fail | 59877394611771566070973661045407778045153191348041417654285895460837817501513 | 919 |
UVM_ERROR @ 89151535 ps: (otp_ctrl_scoreboard.sv:1321) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 32 [0x20]) reg name: otp_ctrl_core_reg_block.direct_access_rdata_0
UVM_INFO @ 89151535 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
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| UVM_FATAL (csr_utils_pkg.sv:618) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout otp_ctrl_core_reg_block.status.dai_idle (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=4) | ||||
| otp_ctrl_macro_errs | 67193882312776399536948052024518814917948959504307735550854444943804525955074 | 1960414 |
UVM_FATAL @ 20050689421 ps: (csr_utils_pkg.sv:618) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout otp_ctrl_core_reg_block.status.dai_idle (addr=0x53dd0010, Comparison=CompareOpEq, exp_data=0x1, call_count=4)
UVM_INFO @ 20050689421 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
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| UVM_ERROR (cip_base_scoreboard.sv:632) [scoreboard] Check failed item.d_data == exp_data (* [*] vs * [*]) d_data mismatch when d_error = * | ||||
| otp_ctrl_stress_all_with_rand_reset | 85418003494690089171345657145792879435262211800432669850875885283975230452408 | 113 |
UVM_ERROR @ 31238169 ps: (cip_base_scoreboard.sv:632) [uvm_test_top.env.scoreboard] Check failed item.d_data == exp_data (0 [0x0] vs 4294967295 [0xffffffff]) d_data mismatch when d_error = 1
UVM_INFO @ 31238169 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
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| UVM_FATAL (csr_utils_pkg.sv:618) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout otp_ctrl_core_reg_block.status.dai_idle (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=1) | ||||
| otp_ctrl_sec_cm | 19104891239922944441019122248749137495314093343490911197713354236721901371155 | 114 |
UVM_FATAL @ 20032505417 ps: (csr_utils_pkg.sv:618) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout otp_ctrl_core_reg_block.status.dai_idle (addr=0xe3bd8010, Comparison=CompareOpEq, exp_data=0x1, call_count=1)
UVM_INFO @ 20032505417 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
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| Job killed most likely because its dependent job failed. | ||||
| otp_ctrl | None | None | ||
| otp_ctrl | None | None | ||