Simulation Results: rom_ctrl/64kb

 
06/04/2026 16:07:05 DVSim: v1.17.3 sha: d2f24af json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 94.54 %
  • code
  • 94.12 %
  • assert
  • 96.79 %
  • func
  • 92.71 %
  • block
  • 95.61 %
  • line
  • 95.77 %
  • branch
  • 93.82 %
  • toggle
  • 86.90 %
  • FSM
  • 100.00 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
rom_ctrl_smoke 5.000s 762.656us 1 1 100.00
csr_hw_reset 1 1 100.00
rom_ctrl_csr_hw_reset 10.000s 1121.029us 1 1 100.00
csr_rw 1 1 100.00
rom_ctrl_csr_rw 5.000s 302.982us 1 1 100.00
csr_bit_bash 1 1 100.00
rom_ctrl_csr_bit_bash 6.000s 293.259us 1 1 100.00
csr_aliasing 1 1 100.00
rom_ctrl_csr_aliasing 5.000s 397.045us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
rom_ctrl_csr_mem_rw_with_rand_reset 5.000s 1055.237us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
rom_ctrl_csr_rw 5.000s 302.982us 1 1 100.00
rom_ctrl_csr_aliasing 5.000s 397.045us 1 1 100.00
mem_walk 1 1 100.00
rom_ctrl_mem_walk 4.000s 384.106us 1 1 100.00
mem_partial_access 1 1 100.00
rom_ctrl_mem_partial_access 6.000s 381.042us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
max_throughput_chk 1 1 100.00
rom_ctrl_max_throughput_chk 5.000s 745.575us 1 1 100.00
stress_all 1 1 100.00
rom_ctrl_stress_all 13.000s 1126.787us 1 1 100.00
kmac_err_chk 1 1 100.00
rom_ctrl_kmac_err_chk 12.000s 2011.475us 1 1 100.00
alert_test 1 1 100.00
rom_ctrl_alert_test 5.000s 294.624us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
rom_ctrl_tl_errors 6.000s 708.647us 1 1 100.00
tl_d_illegal_access 1 1 100.00
rom_ctrl_tl_errors 6.000s 708.647us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
rom_ctrl_csr_hw_reset 10.000s 1121.029us 1 1 100.00
rom_ctrl_csr_rw 5.000s 302.982us 1 1 100.00
rom_ctrl_csr_aliasing 5.000s 397.045us 1 1 100.00
rom_ctrl_same_csr_outstanding 8.000s 4127.994us 1 1 100.00
tl_d_partial_access 4 4 100.00
rom_ctrl_csr_hw_reset 10.000s 1121.029us 1 1 100.00
rom_ctrl_csr_rw 5.000s 302.982us 1 1 100.00
rom_ctrl_csr_aliasing 5.000s 397.045us 1 1 100.00
rom_ctrl_same_csr_outstanding 8.000s 4127.994us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
corrupt_sig_fatal_chk 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 46.000s 8633.728us 1 1 100.00
passthru_mem_tl_intg_err 1 1 100.00
rom_ctrl_passthru_mem_tl_intg_err 22.000s 1265.731us 1 1 100.00
tl_intg_err 2 2 100.00
rom_ctrl_tl_intg_err 24.000s 1274.295us 1 1 100.00
rom_ctrl_sec_cm 197.000s 2918.437us 1 1 100.00
prim_fsm_check 1 1 100.00
rom_ctrl_sec_cm 197.000s 2918.437us 1 1 100.00
prim_count_check 1 1 100.00
rom_ctrl_sec_cm 197.000s 2918.437us 1 1 100.00
sec_cm_checker_ctr_consistency 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 46.000s 8633.728us 1 1 100.00
sec_cm_checker_ctrl_flow_consistency 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 46.000s 8633.728us 1 1 100.00
sec_cm_checker_fsm_local_esc 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 46.000s 8633.728us 1 1 100.00
sec_cm_compare_ctrl_flow_consistency 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 46.000s 8633.728us 1 1 100.00
sec_cm_compare_ctr_consistency 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 46.000s 8633.728us 1 1 100.00
sec_cm_compare_ctr_redun 1 1 100.00
rom_ctrl_sec_cm 197.000s 2918.437us 1 1 100.00
sec_cm_fsm_sparse 1 1 100.00
rom_ctrl_sec_cm 197.000s 2918.437us 1 1 100.00
sec_cm_mem_scramble 1 1 100.00
rom_ctrl_smoke 5.000s 762.656us 1 1 100.00
sec_cm_mem_digest 1 1 100.00
rom_ctrl_smoke 5.000s 762.656us 1 1 100.00
sec_cm_intersig_mubi 1 1 100.00
rom_ctrl_smoke 5.000s 762.656us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
rom_ctrl_tl_intg_err 24.000s 1274.295us 1 1 100.00
sec_cm_bus_local_esc 2 2 100.00
rom_ctrl_corrupt_sig_fatal_chk 46.000s 8633.728us 1 1 100.00
rom_ctrl_kmac_err_chk 12.000s 2011.475us 1 1 100.00
sec_cm_mux_mubi 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 46.000s 8633.728us 1 1 100.00
sec_cm_mux_consistency 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 46.000s 8633.728us 1 1 100.00
sec_cm_ctrl_redun 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 46.000s 8633.728us 1 1 100.00
sec_cm_ctrl_mem_integrity 1 1 100.00
rom_ctrl_passthru_mem_tl_intg_err 22.000s 1265.731us 1 1 100.00
sec_cm_tlul_fifo_ctr_redun 1 1 100.00
rom_ctrl_sec_cm 197.000s 2918.437us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 1 1 100.00
rom_ctrl_stress_all_with_rand_reset 65.000s 3370.509us 1 1 100.00