Simulation Results: rstmgr

 
06/04/2026 16:07:05 DVSim: v1.17.3 sha: d2f24af json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 90.97 %
  • code
  • 79.45 %
  • assert
  • 95.51 %
  • func
  • 97.96 %
  • block
  • 90.51 %
  • line
  • 89.91 %
  • branch
  • 82.93 %
  • toggle
  • 96.90 %
  • FSM
  • 48.05 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
rstmgr_smoke 2.000s 72.011us 1 1 100.00
csr_hw_reset 1 1 100.00
rstmgr_csr_hw_reset 1.000s 64.695us 1 1 100.00
csr_rw 1 1 100.00
rstmgr_csr_rw 1.000s 36.339us 1 1 100.00
csr_bit_bash 1 1 100.00
rstmgr_csr_bit_bash 3.000s 51.627us 1 1 100.00
csr_aliasing 1 1 100.00
rstmgr_csr_aliasing 1.000s 37.926us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
rstmgr_csr_mem_rw_with_rand_reset 1.000s 66.873us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
rstmgr_csr_rw 1.000s 36.339us 1 1 100.00
rstmgr_csr_aliasing 1.000s 37.926us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
reset_stretcher 1 1 100.00
rstmgr_por_stretcher 2.000s 125.426us 1 1 100.00
sw_rst 1 1 100.00
rstmgr_sw_rst 1.000s 37.755us 1 1 100.00
sw_rst_reset_race 1 1 100.00
rstmgr_sw_rst_reset_race 2.000s 86.389us 1 1 100.00
reset_info 1 1 100.00
rstmgr_reset 6.000s 587.465us 1 1 100.00
cpu_info 1 1 100.00
rstmgr_reset 6.000s 587.465us 1 1 100.00
alert_info 1 1 100.00
rstmgr_reset 6.000s 587.465us 1 1 100.00
reset_info_capture 1 1 100.00
rstmgr_reset 6.000s 587.465us 1 1 100.00
stress_all 1 1 100.00
rstmgr_stress_all 1.000s 40.513us 1 1 100.00
alert_test 1 1 100.00
rstmgr_alert_test 2.000s 50.074us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
rstmgr_tl_errors 1.000s 44.739us 1 1 100.00
tl_d_illegal_access 1 1 100.00
rstmgr_tl_errors 1.000s 44.739us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
rstmgr_csr_hw_reset 1.000s 64.695us 1 1 100.00
rstmgr_csr_rw 1.000s 36.339us 1 1 100.00
rstmgr_csr_aliasing 1.000s 37.926us 1 1 100.00
rstmgr_same_csr_outstanding 1.000s 37.462us 1 1 100.00
tl_d_partial_access 4 4 100.00
rstmgr_csr_hw_reset 1.000s 64.695us 1 1 100.00
rstmgr_csr_rw 1.000s 36.339us 1 1 100.00
rstmgr_csr_aliasing 1.000s 37.926us 1 1 100.00
rstmgr_same_csr_outstanding 1.000s 37.462us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
rstmgr_tl_intg_err 2.000s 679.248us 1 1 100.00
rstmgr_sec_cm 18.000s 3408.829us 1 1 100.00
prim_count_check 1 1 100.00
rstmgr_sec_cm 18.000s 3408.829us 1 1 100.00
prim_fsm_check 1 1 100.00
rstmgr_sec_cm 18.000s 3408.829us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
rstmgr_tl_intg_err 2.000s 679.248us 1 1 100.00
sec_cm_scan_intersig_mubi 1 1 100.00
rstmgr_sec_cm_scan_intersig_mubi 2.000s 65.819us 1 1 100.00
sec_cm_leaf_rst_bkgn_chk 1 1 100.00
rstmgr_leaf_rst_cnsty 5.000s 444.167us 1 1 100.00
sec_cm_leaf_rst_shadow 1 1 100.00
rstmgr_leaf_rst_shadow_attack 2.000s 290.680us 1 1 100.00
sec_cm_leaf_fsm_sparse 1 1 100.00
rstmgr_sec_cm 18.000s 3408.829us 1 1 100.00
sec_cm_sw_rst_config_regwen 1 1 100.00
rstmgr_csr_rw 1.000s 36.339us 1 1 100.00
sec_cm_dump_ctrl_config_regwen 1 1 100.00
rstmgr_csr_rw 1.000s 36.339us 1 1 100.00