Simulation Results

Simulation Results: spi_device/1r1w

06/04/2026 16:07:05 DVSim: v1.17.3 sha: d2f24af json Branch: master Tool: xcelium [unknown]

Coverage statistics

Total
85.02 %

code
91.40 %

assert
94.64 %

func
69.01 %

block
98.36 %

line
98.78 %

branch
97.02 %

toggle
81.25 %

FSM
88.54 %

Validation stages

V1		100.00%
V2		92.31%
V2S		100.00%
unmapped		100.00%

8/8 passed

100.00 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
smoke				1	1	100.00
	spi_device_flash_and_tpm	61.000s	8134.289us	1	1	100.00
csr_hw_reset				1	1	100.00
	spi_device_csr_hw_reset	2.000s	163.643us	1	1	100.00
csr_rw				1	1	100.00
	spi_device_csr_rw	2.000s	155.038us	1	1	100.00
csr_bit_bash				1	1	100.00
	spi_device_csr_bit_bash	34.000s	543.862us	1	1	100.00
csr_aliasing				1	1	100.00
	spi_device_csr_aliasing	8.000s	851.982us	1	1	100.00
csr_mem_rw_with_rand_reset				1	1	100.00
	spi_device_csr_mem_rw_with_rand_reset	2.000s	74.851us	1	1	100.00
regwen_csr_and_corresponding_lockable_csr				2	2	100.00
	spi_device_csr_rw	2.000s	155.038us	1	1	100.00
	spi_device_csr_aliasing	8.000s	851.982us	1	1	100.00
mem_walk				1	1	100.00
	spi_device_mem_walk	2.000s	36.216us	1	1	100.00
mem_partial_access				1	1	100.00
	spi_device_mem_partial_access	3.000s	288.974us	1	1	100.00

24/26 passed

92.31 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
csb_read				1	1	100.00
	spi_device_csb_read	2.000s	29.564us	1	1	100.00
mem_parity				0	1	0.00
	spi_device_mem_parity	1.000s	3.306us	0	1	0.00
mem_cfg				0	1	0.00
	spi_device_ram_cfg	1.000s	3.224us	0	1	0.00
tpm_read				1	1	100.00
	spi_device_tpm_rw	3.000s	86.433us	1	1	100.00
tpm_write				1	1	100.00
	spi_device_tpm_rw	3.000s	86.433us	1	1	100.00
tpm_hw_reg				2	2	100.00
	spi_device_tpm_read_hw_reg	9.000s	3149.345us	1	1	100.00
	spi_device_tpm_sts_read	1.000s	98.042us	1	1	100.00
tpm_fully_random_case				1	1	100.00
	spi_device_tpm_all	56.000s	22987.532us	1	1	100.00
pass_cmd_filtering				2	2	100.00
	spi_device_pass_cmd_filtering	12.000s	840.902us	1	1	100.00
	spi_device_flash_all	172.000s	31125.308us	1	1	100.00
pass_addr_translation				2	2	100.00
	spi_device_pass_addr_payload_swap	5.000s	1418.870us	1	1	100.00
	spi_device_flash_all	172.000s	31125.308us	1	1	100.00
pass_payload_translation				2	2	100.00
	spi_device_pass_addr_payload_swap	5.000s	1418.870us	1	1	100.00
	spi_device_flash_all	172.000s	31125.308us	1	1	100.00
cmd_info_slots				1	1	100.00
	spi_device_flash_all	172.000s	31125.308us	1	1	100.00
cmd_read_status				2	2	100.00
	spi_device_intercept	17.000s	9098.105us	1	1	100.00
	spi_device_flash_all	172.000s	31125.308us	1	1	100.00
cmd_read_jedec				2	2	100.00
	spi_device_intercept	17.000s	9098.105us	1	1	100.00
	spi_device_flash_all	172.000s	31125.308us	1	1	100.00
cmd_read_sfdp				2	2	100.00
	spi_device_intercept	17.000s	9098.105us	1	1	100.00
	spi_device_flash_all	172.000s	31125.308us	1	1	100.00
cmd_fast_read				2	2	100.00
	spi_device_intercept	17.000s	9098.105us	1	1	100.00
	spi_device_flash_all	172.000s	31125.308us	1	1	100.00
cmd_read_pipeline				2	2	100.00
	spi_device_intercept	17.000s	9098.105us	1	1	100.00
	spi_device_flash_all	172.000s	31125.308us	1	1	100.00
flash_cmd_upload				1	1	100.00
	spi_device_upload	10.000s	3684.422us	1	1	100.00
mailbox_command				1	1	100.00
	spi_device_mailbox	16.000s	1475.484us	1	1	100.00
mailbox_cross_outside_command				1	1	100.00
	spi_device_mailbox	16.000s	1475.484us	1	1	100.00
mailbox_cross_inside_command				1	1	100.00
	spi_device_mailbox	16.000s	1475.484us	1	1	100.00
cmd_read_buffer				2	2	100.00
	spi_device_flash_mode	37.000s	5693.239us	1	1	100.00
	spi_device_read_buffer_direct	19.000s	1252.262us	1	1	100.00
cmd_dummy_cycle				2	2	100.00
	spi_device_mailbox	16.000s	1475.484us	1	1	100.00
	spi_device_flash_all	172.000s	31125.308us	1	1	100.00
quad_spi				1	1	100.00
	spi_device_flash_all	172.000s	31125.308us	1	1	100.00
dual_spi				1	1	100.00
	spi_device_flash_all	172.000s	31125.308us	1	1	100.00
4b_3b_feature				1	1	100.00
	spi_device_cfg_cmd	3.000s	77.333us	1	1	100.00
write_enable_disable				1	1	100.00
	spi_device_cfg_cmd	3.000s	77.333us	1	1	100.00
TPM_with_flash_or_passthrough_mode				1	1	100.00
	spi_device_flash_and_tpm	61.000s	8134.289us	1	1	100.00
tpm_and_flash_trans_with_min_inactive_time				1	1	100.00
	spi_device_flash_and_tpm_min_idle	150.000s	30406.257us	1	1	100.00
stress_all				1	1	100.00
	spi_device_stress_all	35.000s	1693.755us	1	1	100.00
alert_test				1	1	100.00
	spi_device_alert_test	2.000s	79.965us	1	1	100.00
intr_test				1	1	100.00
	spi_device_intr_test	1.000s	13.193us	1	1	100.00
tl_d_oob_addr_access				1	1	100.00
	spi_device_tl_errors	3.000s	38.985us	1	1	100.00
tl_d_illegal_access				1	1	100.00
	spi_device_tl_errors	3.000s	38.985us	1	1	100.00
tl_d_outstanding_access				4	4	100.00
	spi_device_csr_hw_reset	2.000s	163.643us	1	1	100.00
	spi_device_csr_rw	2.000s	155.038us	1	1	100.00
	spi_device_csr_aliasing	8.000s	851.982us	1	1	100.00
	spi_device_same_csr_outstanding	4.000s	429.635us	1	1	100.00
tl_d_partial_access				4	4	100.00
	spi_device_csr_hw_reset	2.000s	163.643us	1	1	100.00
	spi_device_csr_rw	2.000s	155.038us	1	1	100.00
	spi_device_csr_aliasing	8.000s	851.982us	1	1	100.00
	spi_device_same_csr_outstanding	4.000s	429.635us	1	1	100.00

V2S

2/2 passed

100.00 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
tl_intg_err				2	2	100.00
	spi_device_sec_cm	2.000s	41.904us	1	1	100.00
	spi_device_tl_intg_err	8.000s	395.418us	1	1	100.00
sec_cm_bus_integrity				1	1	100.00
	spi_device_tl_intg_err	8.000s	395.418us	1	1	100.00

unmapped

1/1 passed

100.00 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
Unmapped				1	1	100.00
	spi_device_flash_mode_ignore_cmds	26.000s	2538.913us	1	1	100.00

Error Messages

	Test	seed	line	log context
UVM_ERROR (uvm_hdl_inca.c:743) [UVM/DPI/NOBJ1] name tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.mem[*] cannot be resolved to a hdl object (vlog,vhdl,vlog-slice)
	spi_device_mem_parity	96789146608493945876958700549546941364804298962898513318562374430321785621403	87	UVM_ERROR @ 1653266 ps: (uvm_hdl_inca.c:743) [UVM/DPI/NOBJ1] name tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.mem[98] cannot be resolved to a hdl object (vlog,vhdl,vlog-slice) UVM_ERROR @ 1653266 ps: (spi_device_mem_parity_vseq.sv:44) [uvm_test_top.env.virtual_sequencer.spi_device_mem_parity_vseq] Check failed (uvm_hdl_read(egress_path, mem_data)) ERROR: VHPI NOTFOUND Name tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.mem[994] not found within the scope . UVM_ERROR @ 1653266 ps: (uvm_hdl_inca.c:743) [UVM/DPI/NOBJ2] name tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.mem[994] cannot be resolved to a hdl object (vlog,vhdl,vlog-slice)
UVM_ERROR (spi_device_ram_cfg_vseq.sv:27) [spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (* [] vs [*])
	spi_device_ram_cfg	23318018549103655694195533107020536938540568543697040794828536896240137107235	85	UVM_ERROR @ 939820 ps: (spi_device_ram_cfg_vseq.sv:27) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (0xbf7de5 [101111110111110111100101] vs 0x0 [0]) UVM_ERROR @ 990820 ps: (spi_device_ram_cfg_vseq.sv:27) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (0x169ff9 [101101001111111111001] vs 0x0 [0]) UVM_ERROR @ 1019820 ps: (spi_device_ram_cfg_vseq.sv:27) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (0xbe5896 [101111100101100010010110] vs 0x0 [0]) UVM_ERROR @ 1087820 ps: (spi_device_ram_cfg_vseq.sv:27) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (0xca9bc5 [110010101001101111000101] vs 0x0 [0]) UVM_ERROR @ 1090820 ps: (spi_device_ram_cfg_vseq.sv:27) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (0xc7ce66 [110001111100111001100110] vs 0x0 [0])