Simulation Results: spi_host

 
06/04/2026 16:07:05 DVSim: v1.17.3 sha: d2f24af json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 92.83 %
  • code
  • 95.03 %
  • assert
  • 95.64 %
  • func
  • 87.82 %
  • block
  • 96.96 %
  • line
  • 98.76 %
  • branch
  • 93.35 %
  • toggle
  • 88.02 %
  • FSM
  • 100.00 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
unmapped
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
spi_host_smoke 14.000s 928.331us 1 1 100.00
csr_hw_reset 1 1 100.00
spi_host_csr_hw_reset 2.000s 55.613us 1 1 100.00
csr_rw 1 1 100.00
spi_host_csr_rw 1.000s 20.637us 1 1 100.00
csr_bit_bash 1 1 100.00
spi_host_csr_bit_bash 2.000s 58.496us 1 1 100.00
csr_aliasing 1 1 100.00
spi_host_csr_aliasing 2.000s 66.153us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
spi_host_csr_mem_rw_with_rand_reset 2.000s 34.723us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
spi_host_csr_rw 1.000s 20.637us 1 1 100.00
spi_host_csr_aliasing 2.000s 66.153us 1 1 100.00
mem_walk 1 1 100.00
spi_host_mem_walk 1.000s 21.899us 1 1 100.00
mem_partial_access 1 1 100.00
spi_host_mem_partial_access 1.000s 21.511us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
performance 1 1 100.00
spi_host_performance 2.000s 20.624us 1 1 100.00
error_event_intr 3 3 100.00
spi_host_overflow_underflow 3.000s 298.074us 1 1 100.00
spi_host_error_cmd 2.000s 46.900us 1 1 100.00
spi_host_event 45.000s 3265.941us 1 1 100.00
clock_rate 1 1 100.00
spi_host_speed 1.000s 27.048us 1 1 100.00
speed 1 1 100.00
spi_host_speed 1.000s 27.048us 1 1 100.00
chip_select_timing 1 1 100.00
spi_host_speed 1.000s 27.048us 1 1 100.00
sw_reset 1 1 100.00
spi_host_sw_reset 3.000s 54.955us 1 1 100.00
passthrough_mode 1 1 100.00
spi_host_passthrough_mode 1.000s 29.807us 1 1 100.00
cpol_cpha 1 1 100.00
spi_host_speed 1.000s 27.048us 1 1 100.00
full_cycle 1 1 100.00
spi_host_speed 1.000s 27.048us 1 1 100.00
duplex 1 1 100.00
spi_host_smoke 14.000s 928.331us 1 1 100.00
tx_rx_only 1 1 100.00
spi_host_smoke 14.000s 928.331us 1 1 100.00
stress_all 1 1 100.00
spi_host_stress_all 17.000s 3633.180us 1 1 100.00
spien 1 1 100.00
spi_host_spien 4.000s 1692.681us 1 1 100.00
stall 1 1 100.00
spi_host_status_stall 62.000s 12908.132us 1 1 100.00
Idlecsbactive 1 1 100.00
spi_host_idlecsbactive 7.000s 340.777us 1 1 100.00
data_fifo_status 1 1 100.00
spi_host_overflow_underflow 3.000s 298.074us 1 1 100.00
alert_test 1 1 100.00
spi_host_alert_test 1.000s 45.428us 1 1 100.00
intr_test 1 1 100.00
spi_host_intr_test 2.000s 91.215us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
spi_host_tl_errors 2.000s 63.101us 1 1 100.00
tl_d_illegal_access 1 1 100.00
spi_host_tl_errors 2.000s 63.101us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
spi_host_csr_hw_reset 2.000s 55.613us 1 1 100.00
spi_host_csr_rw 1.000s 20.637us 1 1 100.00
spi_host_csr_aliasing 2.000s 66.153us 1 1 100.00
spi_host_same_csr_outstanding 1.000s 56.491us 1 1 100.00
tl_d_partial_access 4 4 100.00
spi_host_csr_hw_reset 2.000s 55.613us 1 1 100.00
spi_host_csr_rw 1.000s 20.637us 1 1 100.00
spi_host_csr_aliasing 2.000s 66.153us 1 1 100.00
spi_host_same_csr_outstanding 1.000s 56.491us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
spi_host_sec_cm 1.000s 41.463us 1 1 100.00
spi_host_tl_intg_err 1.000s 208.428us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
spi_host_tl_intg_err 1.000s 208.428us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
Unmapped 1 1 100.00
spi_host_upper_range_clkdiv 93.000s 6654.253us 1 1 100.00