Simulation Results

Simulation Results: sram_ctrl/main

06/04/2026 16:07:05 DVSim: v1.17.3 sha: d2f24af json Branch: master Tool: xcelium [unknown]

Coverage statistics

Total
90.27 %

code
83.07 %

assert
95.54 %

func
92.20 %

block
93.76 %

line
94.64 %

branch
88.74 %

toggle
82.24 %

FSM
66.67 %

Validation stages

V1		100.00%
V2		90.00%
V2S		90.00%
V3		100.00%

8/8 passed

100.00 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
smoke				1	1	100.00
	sram_ctrl_smoke	14.000s	3140.792us	1	1	100.00
csr_hw_reset				1	1	100.00
	sram_ctrl_csr_hw_reset	1.000s	19.654us	1	1	100.00
csr_rw				1	1	100.00
	sram_ctrl_csr_rw	2.000s	18.907us	1	1	100.00
csr_bit_bash				1	1	100.00
	sram_ctrl_csr_bit_bash	2.000s	132.314us	1	1	100.00
csr_aliasing				1	1	100.00
	sram_ctrl_csr_aliasing	1.000s	43.281us	1	1	100.00
csr_mem_rw_with_rand_reset				1	1	100.00
	sram_ctrl_csr_mem_rw_with_rand_reset	3.000s	347.788us	1	1	100.00
regwen_csr_and_corresponding_lockable_csr				2	2	100.00
	sram_ctrl_csr_rw	2.000s	18.907us	1	1	100.00
	sram_ctrl_csr_aliasing	1.000s	43.281us	1	1	100.00
mem_walk				1	1	100.00
	sram_ctrl_mem_walk	223.000s	35106.095us	1	1	100.00
mem_partial_access				1	1	100.00
	sram_ctrl_mem_partial_access	54.000s	4823.802us	1	1	100.00

18/20 passed

90.00 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
multiple_keys				1	1	100.00
	sram_ctrl_multiple_keys	698.000s	26897.321us	1	1	100.00
stress_pipeline				1	1	100.00
	sram_ctrl_stress_pipeline	206.000s	13618.895us	1	1	100.00
bijection				1	1	100.00
	sram_ctrl_bijection	1418.000s	105628.527us	1	1	100.00
access_during_key_req				1	1	100.00
	sram_ctrl_access_during_key_req	130.000s	4202.522us	1	1	100.00
lc_escalation				1	1	100.00
	sram_ctrl_lc_escalation	11.000s	6676.090us	1	1	100.00
executable				1	1	100.00
	sram_ctrl_executable	229.000s	36907.130us	1	1	100.00
partial_access				2	2	100.00
	sram_ctrl_partial_access	43.000s	1333.824us	1	1	100.00
	sram_ctrl_partial_access_b2b	216.000s	7202.706us	1	1	100.00
max_throughput				1	3	33.33
	sram_ctrl_max_throughput	3.000s	726.252us	0	1	0.00
	sram_ctrl_throughput_w_partial_write	5.000s	722.038us	1	1	100.00
	sram_ctrl_throughput_w_readback	6.000s	2742.372us	0	1	0.00
regwen				1	1	100.00
	sram_ctrl_regwen	165.000s	29039.674us	1	1	100.00
ram_cfg				1	1	100.00
	sram_ctrl_ram_cfg	3.000s	1437.591us	1	1	100.00
stress_all				1	1	100.00
	sram_ctrl_stress_all	2254.000s	84660.535us	1	1	100.00
alert_test				1	1	100.00
	sram_ctrl_alert_test	1.000s	43.074us	1	1	100.00
tl_d_oob_addr_access				1	1	100.00
	sram_ctrl_tl_errors	2.000s	62.378us	1	1	100.00
tl_d_illegal_access				1	1	100.00
	sram_ctrl_tl_errors	2.000s	62.378us	1	1	100.00
tl_d_outstanding_access				4	4	100.00
	sram_ctrl_csr_hw_reset	1.000s	19.654us	1	1	100.00
	sram_ctrl_csr_rw	2.000s	18.907us	1	1	100.00
	sram_ctrl_csr_aliasing	1.000s	43.281us	1	1	100.00
	sram_ctrl_same_csr_outstanding	1.000s	72.538us	1	1	100.00
tl_d_partial_access				4	4	100.00
	sram_ctrl_csr_hw_reset	1.000s	19.654us	1	1	100.00
	sram_ctrl_csr_rw	2.000s	18.907us	1	1	100.00
	sram_ctrl_csr_aliasing	1.000s	43.281us	1	1	100.00
	sram_ctrl_same_csr_outstanding	1.000s	72.538us	1	1	100.00

V2S

9/10 passed

90.00 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
passthru_mem_tl_intg_err				1	1	100.00
	sram_ctrl_passthru_mem_tl_intg_err	21.000s	7200.629us	1	1	100.00
tl_intg_err				1	2	50.00
	sram_ctrl_sec_cm	1.000s	10.104us	0	1	0.00
	sram_ctrl_tl_intg_err	3.000s	1135.809us	1	1	100.00
prim_count_check				0	1	0.00
	sram_ctrl_sec_cm	1.000s	10.104us	0	1	0.00
sec_cm_bus_integrity				1	1	100.00
	sram_ctrl_tl_intg_err	3.000s	1135.809us	1	1	100.00
sec_cm_ctrl_config_regwen				1	1	100.00
	sram_ctrl_regwen	165.000s	29039.674us	1	1	100.00
sec_cm_readback_config_regwen				1	1	100.00
	sram_ctrl_regwen	165.000s	29039.674us	1	1	100.00
sec_cm_exec_config_regwen				1	1	100.00
	sram_ctrl_csr_rw	2.000s	18.907us	1	1	100.00
sec_cm_exec_config_mubi				1	1	100.00
	sram_ctrl_executable	229.000s	36907.130us	1	1	100.00
sec_cm_exec_intersig_mubi				1	1	100.00
	sram_ctrl_executable	229.000s	36907.130us	1	1	100.00
sec_cm_lc_hw_debug_en_intersig_mubi				1	1	100.00
	sram_ctrl_executable	229.000s	36907.130us	1	1	100.00
sec_cm_lc_escalate_en_intersig_mubi				1	1	100.00
	sram_ctrl_lc_escalation	11.000s	6676.090us	1	1	100.00
sec_cm_prim_ram_ctrl_mubi				1	1	100.00
	sram_ctrl_mubi_enc_err	4.000s	4455.258us	1	1	100.00
sec_cm_mem_integrity				1	1	100.00
	sram_ctrl_passthru_mem_tl_intg_err	21.000s	7200.629us	1	1	100.00
sec_cm_mem_readback				1	1	100.00
	sram_ctrl_readback_err	5.000s	669.108us	1	1	100.00
sec_cm_mem_scramble				1	1	100.00
	sram_ctrl_smoke	14.000s	3140.792us	1	1	100.00
sec_cm_addr_scramble				1	1	100.00
	sram_ctrl_smoke	14.000s	3140.792us	1	1	100.00
sec_cm_instr_bus_lc_gated				1	1	100.00
	sram_ctrl_executable	229.000s	36907.130us	1	1	100.00
sec_cm_ram_tl_lc_gate_fsm_sparse				0	1	0.00
	sram_ctrl_sec_cm	1.000s	10.104us	0	1	0.00
sec_cm_key_global_esc				1	1	100.00
	sram_ctrl_lc_escalation	11.000s	6676.090us	1	1	100.00
sec_cm_key_local_esc				0	1	0.00
	sram_ctrl_sec_cm	1.000s	10.104us	0	1	0.00
sec_cm_init_ctr_redun				0	1	0.00
	sram_ctrl_sec_cm	1.000s	10.104us	0	1	0.00
sec_cm_scramble_key_sideload				1	1	100.00
	sram_ctrl_smoke	14.000s	3140.792us	1	1	100.00
sec_cm_tlul_fifo_ctr_redun				0	1	0.00
	sram_ctrl_sec_cm	1.000s	10.104us	0	1	0.00

1/1 passed

100.00 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
stress_all_with_rand_reset				1	1	100.00
	sram_ctrl_stress_all_with_rand_reset	21.000s	928.684us	1	1	100.00

Error Messages

	Test	seed	line	log context
UVM_FATAL (sram_ctrl_base_vseq.sv:329) [sram_ctrl_throughput_vseq] Check failed (std::randomize(mask) with {$countones(mask ^ {mask[bus_params_pkg::BUS_DBW-:], 'b0}) <= ; mask dist {'* :/ * - partial_access_pct, [* : '* - *] :/ partial_access_pct};}) Randomization failed!
	sram_ctrl_max_throughput	7632661205250733219021246686448597021932018454115528671656671738993452984354	102	UVM_FATAL @ 726251842 ps: (sram_ctrl_base_vseq.sv:329) [uvm_test_top.env.virtual_sequencer.sram_ctrl_throughput_vseq] Check failed (std::randomize(mask) with {$countones(mask ^ {mask[bus_params_pkg::BUS_DBW-2:0], 1'b0}) <= 2; mask dist {'1 :/ 100 - partial_access_pct, [0 : '1 - 1] :/ partial_access_pct};}) Randomization failed! UVM_INFO @ 726251842 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	sram_ctrl_throughput_w_readback	38451324685516534932110573149591113687687797063671465552123345857619235200830	102	UVM_FATAL @ 2742371588 ps: (sram_ctrl_base_vseq.sv:329) [uvm_test_top.env.virtual_sequencer.sram_ctrl_throughput_vseq] Check failed (std::randomize(mask) with {$countones(mask ^ {mask[bus_params_pkg::BUS_DBW-2:0], 1'b0}) <= 2; mask dist {'1 :/ 100 - partial_access_pct, [0 : '1 - 1] :/ partial_access_pct};}) Randomization failed! UVM_INFO @ 2742371588 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
xmsim: E,ASRTST (/nightly/current_run/scratch/master/sram_ctrl_main-sim-xcelium/default/fusesoc-work/src/lowrisc_tlul_common_/rtl/tlul_assert.sv,293): Assertion respMustHaveReq_A has failed
	sram_ctrl_sec_cm	95933157064509327338739048026943068519422898388021349680195228945869551117660	89	xmsim: *E,ASRTST (/nightly/current_run/scratch/master/sram_ctrl_main-sim-xcelium/default/fusesoc-work/src/lowrisc_tlul_common_0.1/rtl/tlul_assert.sv,293): (time 5572413 PS) Assertion tb.dut.tlul_assert_device_ram.gen_device.gen_d2h.respMustHaveReq_A has failed UVM_ERROR @ 10103663 ps: (csr_utils_pkg.sv:458) [csr_utils_pkg::csr_rd_check.isolation_fork.unmblk1] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: sram_ctrl_regs_reg_block.status.init_error reset value: 0x0 UVM_INFO @ 10103663 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---