Simulation Results

Simulation Results: sram_ctrl/ret

06/04/2026 16:07:05 DVSim: v1.17.3 sha: d2f24af json Branch: master Tool: xcelium [unknown]

Coverage statistics

Total
90.72 %

code
82.68 %

assert
95.51 %

func
93.96 %

block
93.00 %

line
93.95 %

branch
87.50 %

toggle
82.61 %

FSM
66.67 %

Validation stages

V1		100.00%
V2		90.00%
V2S		80.00%
V3		100.00%

8/8 passed

100.00 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
smoke				1	1	100.00
	sram_ctrl_smoke	6.000s	170.687us	1	1	100.00
csr_hw_reset				1	1	100.00
	sram_ctrl_csr_hw_reset	1.000s	13.232us	1	1	100.00
csr_rw				1	1	100.00
	sram_ctrl_csr_rw	1.000s	16.029us	1	1	100.00
csr_bit_bash				1	1	100.00
	sram_ctrl_csr_bit_bash	2.000s	46.348us	1	1	100.00
csr_aliasing				1	1	100.00
	sram_ctrl_csr_aliasing	2.000s	58.676us	1	1	100.00
csr_mem_rw_with_rand_reset				1	1	100.00
	sram_ctrl_csr_mem_rw_with_rand_reset	2.000s	68.438us	1	1	100.00
regwen_csr_and_corresponding_lockable_csr				2	2	100.00
	sram_ctrl_csr_rw	1.000s	16.029us	1	1	100.00
	sram_ctrl_csr_aliasing	2.000s	58.676us	1	1	100.00
mem_walk				1	1	100.00
	sram_ctrl_mem_walk	6.000s	284.476us	1	1	100.00
mem_partial_access				1	1	100.00
	sram_ctrl_mem_partial_access	3.000s	91.803us	1	1	100.00

18/20 passed

90.00 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
multiple_keys				1	1	100.00
	sram_ctrl_multiple_keys	473.000s	2725.450us	1	1	100.00
stress_pipeline				1	1	100.00
	sram_ctrl_stress_pipeline	210.000s	20079.852us	1	1	100.00
bijection				1	1	100.00
	sram_ctrl_bijection	26.000s	2611.394us	1	1	100.00
access_during_key_req				1	1	100.00
	sram_ctrl_access_during_key_req	246.000s	4074.143us	1	1	100.00
lc_escalation				1	1	100.00
	sram_ctrl_lc_escalation	6.000s	777.481us	1	1	100.00
executable				1	1	100.00
	sram_ctrl_executable	398.000s	15774.430us	1	1	100.00
partial_access				2	2	100.00
	sram_ctrl_partial_access	46.000s	6278.061us	1	1	100.00
	sram_ctrl_partial_access_b2b	194.000s	32976.487us	1	1	100.00
max_throughput				1	3	33.33
	sram_ctrl_max_throughput	2.000s	99.336us	0	1	0.00
	sram_ctrl_throughput_w_partial_write	48.000s	1211.679us	1	1	100.00
	sram_ctrl_throughput_w_readback	2.000s	247.402us	0	1	0.00
regwen				1	1	100.00
	sram_ctrl_regwen	905.000s	3857.271us	1	1	100.00
ram_cfg				1	1	100.00
	sram_ctrl_ram_cfg	2.000s	88.389us	1	1	100.00
stress_all				1	1	100.00
	sram_ctrl_stress_all	2040.000s	43887.525us	1	1	100.00
alert_test				1	1	100.00
	sram_ctrl_alert_test	1.000s	14.355us	1	1	100.00
tl_d_oob_addr_access				1	1	100.00
	sram_ctrl_tl_errors	4.000s	161.972us	1	1	100.00
tl_d_illegal_access				1	1	100.00
	sram_ctrl_tl_errors	4.000s	161.972us	1	1	100.00
tl_d_outstanding_access				4	4	100.00
	sram_ctrl_csr_hw_reset	1.000s	13.232us	1	1	100.00
	sram_ctrl_csr_rw	1.000s	16.029us	1	1	100.00
	sram_ctrl_csr_aliasing	2.000s	58.676us	1	1	100.00
	sram_ctrl_same_csr_outstanding	1.000s	19.994us	1	1	100.00
tl_d_partial_access				4	4	100.00
	sram_ctrl_csr_hw_reset	1.000s	13.232us	1	1	100.00
	sram_ctrl_csr_rw	1.000s	16.029us	1	1	100.00
	sram_ctrl_csr_aliasing	2.000s	58.676us	1	1	100.00
	sram_ctrl_same_csr_outstanding	1.000s	19.994us	1	1	100.00

V2S

8/10 passed

80.00 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
passthru_mem_tl_intg_err				1	1	100.00
	sram_ctrl_passthru_mem_tl_intg_err	3.000s	2367.611us	1	1	100.00
tl_intg_err				1	2	50.00
	sram_ctrl_tl_intg_err	3.000s	893.790us	1	1	100.00
	sram_ctrl_sec_cm	1.000s	6.701us	0	1	0.00
prim_count_check				0	1	0.00
	sram_ctrl_sec_cm	1.000s	6.701us	0	1	0.00
sec_cm_bus_integrity				1	1	100.00
	sram_ctrl_tl_intg_err	3.000s	893.790us	1	1	100.00
sec_cm_ctrl_config_regwen				1	1	100.00
	sram_ctrl_regwen	905.000s	3857.271us	1	1	100.00
sec_cm_readback_config_regwen				1	1	100.00
	sram_ctrl_regwen	905.000s	3857.271us	1	1	100.00
sec_cm_exec_config_regwen				1	1	100.00
	sram_ctrl_csr_rw	1.000s	16.029us	1	1	100.00
sec_cm_exec_config_mubi				1	1	100.00
	sram_ctrl_executable	398.000s	15774.430us	1	1	100.00
sec_cm_exec_intersig_mubi				1	1	100.00
	sram_ctrl_executable	398.000s	15774.430us	1	1	100.00
sec_cm_lc_hw_debug_en_intersig_mubi				1	1	100.00
	sram_ctrl_executable	398.000s	15774.430us	1	1	100.00
sec_cm_lc_escalate_en_intersig_mubi				1	1	100.00
	sram_ctrl_lc_escalation	6.000s	777.481us	1	1	100.00
sec_cm_prim_ram_ctrl_mubi				0	1	0.00
	sram_ctrl_mubi_enc_err	1.000s	36.990us	0	1	0.00
sec_cm_mem_integrity				1	1	100.00
	sram_ctrl_passthru_mem_tl_intg_err	3.000s	2367.611us	1	1	100.00
sec_cm_mem_readback				1	1	100.00
	sram_ctrl_readback_err	2.000s	52.720us	1	1	100.00
sec_cm_mem_scramble				1	1	100.00
	sram_ctrl_smoke	6.000s	170.687us	1	1	100.00
sec_cm_addr_scramble				1	1	100.00
	sram_ctrl_smoke	6.000s	170.687us	1	1	100.00
sec_cm_instr_bus_lc_gated				1	1	100.00
	sram_ctrl_executable	398.000s	15774.430us	1	1	100.00
sec_cm_ram_tl_lc_gate_fsm_sparse				0	1	0.00
	sram_ctrl_sec_cm	1.000s	6.701us	0	1	0.00
sec_cm_key_global_esc				1	1	100.00
	sram_ctrl_lc_escalation	6.000s	777.481us	1	1	100.00
sec_cm_key_local_esc				0	1	0.00
	sram_ctrl_sec_cm	1.000s	6.701us	0	1	0.00
sec_cm_init_ctr_redun				0	1	0.00
	sram_ctrl_sec_cm	1.000s	6.701us	0	1	0.00
sec_cm_scramble_key_sideload				1	1	100.00
	sram_ctrl_smoke	6.000s	170.687us	1	1	100.00
sec_cm_tlul_fifo_ctr_redun				0	1	0.00
	sram_ctrl_sec_cm	1.000s	6.701us	0	1	0.00

1/1 passed

100.00 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
stress_all_with_rand_reset				1	1	100.00
	sram_ctrl_stress_all_with_rand_reset	4.000s	345.455us	1	1	100.00

Error Messages

	Test	seed	line	log context
UVM_FATAL (sram_ctrl_base_vseq.sv:329) [sram_ctrl_throughput_vseq] Check failed (std::randomize(mask) with {$countones(mask ^ {mask[bus_params_pkg::BUS_DBW-:], 'b0}) <= ; mask dist {'* :/ * - partial_access_pct, [* : '* - *] :/ partial_access_pct};}) Randomization failed!
	sram_ctrl_max_throughput	90333428705187109570840242051110268557339878852187967005564302957297276332330	102	UVM_FATAL @ 99336349 ps: (sram_ctrl_base_vseq.sv:329) [uvm_test_top.env.virtual_sequencer.sram_ctrl_throughput_vseq] Check failed (std::randomize(mask) with {$countones(mask ^ {mask[bus_params_pkg::BUS_DBW-2:0], 1'b0}) <= 2; mask dist {'1 :/ 100 - partial_access_pct, [0 : '1 - 1] :/ partial_access_pct};}) Randomization failed! UVM_INFO @ 99336349 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	sram_ctrl_throughput_w_readback	11280011596264107130979108346370233890635300309982222194273893783378916219586	102	UVM_FATAL @ 247402363 ps: (sram_ctrl_base_vseq.sv:329) [uvm_test_top.env.virtual_sequencer.sram_ctrl_throughput_vseq] Check failed (std::randomize(mask) with {$countones(mask ^ {mask[bus_params_pkg::BUS_DBW-2:0], 1'b0}) <= 2; mask dist {'1 :/ 100 - partial_access_pct, [0 : '1 - 1] :/ partial_access_pct};}) Randomization failed! UVM_INFO @ 247402363 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
xmsim: E,ASRTST (/nightly/current_run/scratch/master/sram_ctrl_ret-sim-xcelium/default/fusesoc-work/src/lowrisc_tlul_adapter_sram_/rtl/tlul_adapter_sram.sv,636): Assertion rvalidHighReqFifoEmpty has failed
	sram_ctrl_mubi_enc_err	40839116657305045181383271752925849075098912034643303655058890665644893521731	89	xmsim: *E,ASRTST (/nightly/current_run/scratch/master/sram_ctrl_ret-sim-xcelium/default/fusesoc-work/src/lowrisc_tlul_adapter_sram_0.1/rtl/tlul_adapter_sram.sv,636): (time 36990105 PS) Assertion tb.dut.u_tlul_adapter_sram_racl.tlul_adapter_sram.rvalidHighReqFifoEmpty has failed UVM_ERROR @ 36990105 ps: (tlul_adapter_sram.sv:636) [ASSERT FAILED] rvalidHighReqFifoEmpty UVM_INFO @ 36990105 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR (csr_utils_pkg.sv:458) [csr_utils_pkg::csr_rd_check.isolation_fork.unmblk1] Check failed obs == exp (* [] vs []) Regname: sram_ctrl_regs_reg_block.status.init_error reset value:
	sram_ctrl_sec_cm	7827549276423933825040273956627940787021184096114017618504015554940822906497	93	UVM_ERROR @ 6700826 ps: (csr_utils_pkg.sv:458) [csr_utils_pkg::csr_rd_check.isolation_fork.unmblk1] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: sram_ctrl_regs_reg_block.status.init_error reset value: 0x0 UVM_INFO @ 6700826 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---