Simulation Results

Simulation Results: uart

06/04/2026 16:07:05 DVSim: v1.17.3 sha: d2f24af json Branch: master Tool: xcelium [unknown]

Coverage statistics

Total
88.42 %

code
77.46 %

assert
97.12 %

func
90.69 %

block
98.41 %

line
99.24 %

branch
96.87 %

toggle
88.74 %

FSM
25.00 %

Validation stages

V1		100.00%
V2		95.45%
V2S		100.00%
V3		100.00%

6/6 passed

100.00 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
smoke				1	1	100.00
	uart_smoke	1.000s	486.100us	1	1	100.00
csr_hw_reset				1	1	100.00
	uart_csr_hw_reset	2.000s	201.223us	1	1	100.00
csr_rw				1	1	100.00
	uart_csr_rw	1.000s	52.819us	1	1	100.00
csr_bit_bash				1	1	100.00
	uart_csr_bit_bash	2.000s	356.547us	1	1	100.00
csr_aliasing				1	1	100.00
	uart_csr_aliasing	1.000s	61.410us	1	1	100.00
csr_mem_rw_with_rand_reset				1	1	100.00
	uart_csr_mem_rw_with_rand_reset	1.000s	89.145us	1	1	100.00
regwen_csr_and_corresponding_lockable_csr				2	2	100.00
	uart_csr_rw	1.000s	52.819us	1	1	100.00
	uart_csr_aliasing	1.000s	61.410us	1	1	100.00

21/22 passed

95.45 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
base_random_seq				1	1	100.00
	uart_tx_rx	96.000s	89466.094us	1	1	100.00
parity				2	2	100.00
	uart_smoke	1.000s	486.100us	1	1	100.00
	uart_tx_rx	96.000s	89466.094us	1	1	100.00
parity_error				2	2	100.00
	uart_intr	88.000s	127589.144us	1	1	100.00
	uart_rx_parity_err	257.000s	176238.271us	1	1	100.00
watermark				2	2	100.00
	uart_tx_rx	96.000s	89466.094us	1	1	100.00
	uart_intr	88.000s	127589.144us	1	1	100.00
fifo_full				1	1	100.00
	uart_fifo_full	65.000s	37650.309us	1	1	100.00
fifo_overflow				1	1	100.00
	uart_fifo_overflow	111.000s	80026.555us	1	1	100.00
fifo_reset				1	1	100.00
	uart_fifo_reset	150.000s	57109.697us	1	1	100.00
rx_frame_err				1	1	100.00
	uart_intr	88.000s	127589.144us	1	1	100.00
rx_break_err				1	1	100.00
	uart_intr	88.000s	127589.144us	1	1	100.00
rx_timeout				1	1	100.00
	uart_intr	88.000s	127589.144us	1	1	100.00
perf				1	1	100.00
	uart_perf	162.000s	16286.567us	1	1	100.00
sys_loopback				1	1	100.00
	uart_loopback	3.000s	1120.140us	1	1	100.00
line_loopback				1	1	100.00
	uart_loopback	3.000s	1120.140us	1	1	100.00
rx_noise_filter				1	1	100.00
	uart_noise_filter	12.000s	6727.473us	1	1	100.00
rx_start_bit_filter				1	1	100.00
	uart_rx_start_bit_filter	33.000s	46930.658us	1	1	100.00
tx_overide				1	1	100.00
	uart_tx_ovrd	4.000s	1334.618us	1	1	100.00
rx_oversample				1	1	100.00
	uart_rx_oversample	21.000s	2984.802us	1	1	100.00
long_b2b_transfer				1	1	100.00
	uart_long_xfer_wo_dly	368.000s	180854.097us	1	1	100.00
stress_all				0	1	0.00
	uart_stress_all	150.000s	166294.775us	0	1	0.00
alert_test				1	1	100.00
	uart_alert_test	1.000s	50.060us	1	1	100.00
intr_test				1	1	100.00
	uart_intr_test	1.000s	13.067us	1	1	100.00
tl_d_oob_addr_access				1	1	100.00
	uart_tl_errors	1.000s	110.936us	1	1	100.00
tl_d_illegal_access				1	1	100.00
	uart_tl_errors	1.000s	110.936us	1	1	100.00
tl_d_outstanding_access				4	4	100.00
	uart_csr_hw_reset	2.000s	201.223us	1	1	100.00
	uart_csr_rw	1.000s	52.819us	1	1	100.00
	uart_csr_aliasing	1.000s	61.410us	1	1	100.00
	uart_same_csr_outstanding	2.000s	12.632us	1	1	100.00
tl_d_partial_access				4	4	100.00
	uart_csr_hw_reset	2.000s	201.223us	1	1	100.00
	uart_csr_rw	1.000s	52.819us	1	1	100.00
	uart_csr_aliasing	1.000s	61.410us	1	1	100.00
	uart_same_csr_outstanding	2.000s	12.632us	1	1	100.00

V2S

2/2 passed

100.00 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
tl_intg_err				2	2	100.00
	uart_sec_cm	1.000s	266.005us	1	1	100.00
	uart_tl_intg_err	1.000s	182.655us	1	1	100.00
sec_cm_bus_integrity				1	1	100.00
	uart_tl_intg_err	1.000s	182.655us	1	1	100.00

1/1 passed

100.00 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
stress_all_with_rand_reset				1	1	100.00
	uart_stress_all_with_rand_reset	45.000s	16687.187us	1	1	100.00

Error Messages

	Test	seed	line	log context
UVM_ERROR (uart_scoreboard.sv:395) [scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (* [] vs []) check rx_idle fail: rx_en = , uart_rx_clk_pulses = *
	uart_stress_all	58635448459969398311305519577621516339967576288661658302826525109835306288211	108	UVM_ERROR @ 166264775422 ps: (uart_scoreboard.sv:395) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0 UVM_ERROR @ 166272775414 ps: (uart_scoreboard.sv:395) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0 UVM_ERROR @ 166273411777 ps: (uart_scoreboard.sv:395) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0 UVM_ERROR @ 166273866322 ps: (uart_scoreboard.sv:395) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0 UVM_ERROR @ 166274320867 ps: (uart_scoreboard.sv:395) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0