Simulation Results: ac_range_check

 
07/04/2026 16:08:41 DVSim: v1.17.3 sha: ae672c6 json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 82.87 %
  • code
  • 93.03 %
  • assert
  • 97.75 %
  • func
  • 57.84 %
  • block
  • 99.10 %
  • line
  • 99.93 %
  • branch
  • 98.24 %
  • toggle
  • 80.91 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
V3
100.00%
unmapped
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
ac_range_check_smoke 1 1 100.00
ac_range_check_smoke 31.000s 2714.233us 1 1 100.00
ac_range_check_smoke_racl 1 1 100.00
ac_range_check_smoke_racl 44.000s 2402.129us 1 1 100.00
csr_hw_reset 1 1 100.00
ac_range_check_csr_hw_reset 2.000s 407.904us 1 1 100.00
csr_rw 1 1 100.00
ac_range_check_csr_rw 3.000s 64.160us 1 1 100.00
csr_bit_bash 1 1 100.00
ac_range_check_csr_bit_bash 33.000s 1648.188us 1 1 100.00
csr_aliasing 1 1 100.00
ac_range_check_csr_aliasing 19.000s 4276.251us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
ac_range_check_csr_mem_rw_with_rand_reset 2.000s 121.016us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
ac_range_check_csr_rw 3.000s 64.160us 1 1 100.00
ac_range_check_csr_aliasing 19.000s 4276.251us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
ac_range_check_lock_range 1 1 100.00
ac_range_check_lock_range 3.000s 681.175us 1 1 100.00
ac_range_bypass_enable 1 1 100.00
ac_range_check_bypass 27.000s 1048.012us 1 1 100.00
stress_all 1 1 100.00
ac_range_check_stress_all 174.000s 93269.086us 1 1 100.00
alert_test 1 1 100.00
ac_range_check_alert_test 2.000s 37.725us 1 1 100.00
intr_test 1 1 100.00
ac_range_check_intr_test 2.000s 14.065us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
ac_range_check_tl_errors 3.000s 50.394us 1 1 100.00
tl_d_illegal_access 1 1 100.00
ac_range_check_tl_errors 3.000s 50.394us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
ac_range_check_csr_hw_reset 2.000s 407.904us 1 1 100.00
ac_range_check_csr_rw 3.000s 64.160us 1 1 100.00
ac_range_check_csr_aliasing 19.000s 4276.251us 1 1 100.00
ac_range_check_same_csr_outstanding 4.000s 673.601us 1 1 100.00
tl_d_partial_access 4 4 100.00
ac_range_check_csr_hw_reset 2.000s 407.904us 1 1 100.00
ac_range_check_csr_rw 3.000s 64.160us 1 1 100.00
ac_range_check_csr_aliasing 19.000s 4276.251us 1 1 100.00
ac_range_check_same_csr_outstanding 4.000s 673.601us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
shadow_reg_update_error 1 1 100.00
ac_range_check_shadow_reg_errors 12.000s 7705.018us 1 1 100.00
shadow_reg_read_clear_staged_value 1 1 100.00
ac_range_check_shadow_reg_errors 12.000s 7705.018us 1 1 100.00
shadow_reg_storage_error 1 1 100.00
ac_range_check_shadow_reg_errors 12.000s 7705.018us 1 1 100.00
shadowed_reset_glitch 1 1 100.00
ac_range_check_shadow_reg_errors 12.000s 7705.018us 1 1 100.00
shadow_reg_update_error_with_csr_rw 1 1 100.00
ac_range_check_shadow_reg_errors_with_csr_rw 73.000s 16206.354us 1 1 100.00
tl_intg_err 2 2 100.00
ac_range_check_sec_cm 1.000s 13.385us 1 1 100.00
ac_range_check_tl_intg_err 11.000s 377.403us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 1 1 100.00
ac_range_check_stress_all_with_rand_reset 286.000s 2400.029us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
Unmapped 1 1 100.00
ac_range_check_smoke_high_threshold 28.000s 1045.702us 1 1 100.00