Simulation Results: aes/unmasked

 
07/04/2026 16:08:41 DVSim: v1.17.3 sha: ae672c6 json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 85.52 %
  • code
  • 92.31 %
  • assert
  • 97.75 %
  • func
  • 66.51 %
  • block
  • 92.00 %
  • line
  • 94.18 %
  • branch
  • 85.56 %
  • toggle
  • 97.99 %
  • FSM
  • 91.49 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
V3
0.00%
Testpoint Test Max Runtime Sim Time Pass Total %
wake_up 1 1 100.00
aes_wake_up 2.000s 51.415us 1 1 100.00
smoke 1 1 100.00
aes_smoke 3.000s 117.142us 1 1 100.00
csr_hw_reset 1 1 100.00
aes_csr_hw_reset 2.000s 67.264us 1 1 100.00
csr_rw 1 1 100.00
aes_csr_rw 3.000s 56.804us 1 1 100.00
csr_bit_bash 1 1 100.00
aes_csr_bit_bash 4.000s 346.146us 1 1 100.00
csr_aliasing 1 1 100.00
aes_csr_aliasing 3.000s 137.840us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
aes_csr_mem_rw_with_rand_reset 2.000s 167.343us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
aes_csr_rw 3.000s 56.804us 1 1 100.00
aes_csr_aliasing 3.000s 137.840us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
algorithm 3 3 100.00
aes_smoke 3.000s 117.142us 1 1 100.00
aes_config_error 2.000s 59.546us 1 1 100.00
aes_stress 1.000s 61.047us 1 1 100.00
key_length 3 3 100.00
aes_smoke 3.000s 117.142us 1 1 100.00
aes_config_error 2.000s 59.546us 1 1 100.00
aes_stress 1.000s 61.047us 1 1 100.00
back2back 2 2 100.00
aes_stress 1.000s 61.047us 1 1 100.00
aes_b2b 7.000s 879.209us 1 1 100.00
backpressure 1 1 100.00
aes_stress 1.000s 61.047us 1 1 100.00
multi_message 4 4 100.00
aes_smoke 3.000s 117.142us 1 1 100.00
aes_config_error 2.000s 59.546us 1 1 100.00
aes_stress 1.000s 61.047us 1 1 100.00
aes_alert_reset 2.000s 112.300us 1 1 100.00
failure_test 3 3 100.00
aes_man_cfg_err 2.000s 91.754us 1 1 100.00
aes_config_error 2.000s 59.546us 1 1 100.00
aes_alert_reset 2.000s 112.300us 1 1 100.00
trigger_clear_test 1 1 100.00
aes_clear 3.000s 318.207us 1 1 100.00
nist_test_vectors 1 1 100.00
aes_nist_vectors 4.000s 401.058us 1 1 100.00
nist_test_vectors_gcm 1 1 100.00
aes_nist_vectors_gcm 4.000s 107.114us 1 1 100.00
reset_recovery 1 1 100.00
aes_alert_reset 2.000s 112.300us 1 1 100.00
stress 1 1 100.00
aes_stress 1.000s 61.047us 1 1 100.00
sideload 2 2 100.00
aes_stress 1.000s 61.047us 1 1 100.00
aes_sideload 2.000s 87.845us 1 1 100.00
deinitialization 1 1 100.00
aes_deinit 3.000s 90.435us 1 1 100.00
stress_all 1 1 100.00
aes_stress_all 5.000s 149.713us 1 1 100.00
gcm_save_and_restore 1 1 100.00
aes_gcm_save_restore 3.000s 367.020us 1 1 100.00
alert_test 1 1 100.00
aes_alert_test 2.000s 65.234us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
aes_tl_errors 3.000s 1198.013us 1 1 100.00
tl_d_illegal_access 1 1 100.00
aes_tl_errors 3.000s 1198.013us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
aes_csr_hw_reset 2.000s 67.264us 1 1 100.00
aes_csr_rw 3.000s 56.804us 1 1 100.00
aes_csr_aliasing 3.000s 137.840us 1 1 100.00
aes_same_csr_outstanding 2.000s 74.247us 1 1 100.00
tl_d_partial_access 4 4 100.00
aes_csr_hw_reset 2.000s 67.264us 1 1 100.00
aes_csr_rw 3.000s 56.804us 1 1 100.00
aes_csr_aliasing 3.000s 137.840us 1 1 100.00
aes_same_csr_outstanding 2.000s 74.247us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
reseeding 1 1 100.00
aes_reseed 3.000s 80.874us 1 1 100.00
fault_inject 3 3 100.00
aes_fi 3.000s 134.487us 1 1 100.00
aes_control_fi 3.000s 60.362us 1 1 100.00
aes_cipher_fi 1.000s 45.832us 1 1 100.00
shadow_reg_update_error 1 1 100.00
aes_shadow_reg_errors 2.000s 162.038us 1 1 100.00
shadow_reg_read_clear_staged_value 1 1 100.00
aes_shadow_reg_errors 2.000s 162.038us 1 1 100.00
shadow_reg_storage_error 1 1 100.00
aes_shadow_reg_errors 2.000s 162.038us 1 1 100.00
shadowed_reset_glitch 1 1 100.00
aes_shadow_reg_errors 2.000s 162.038us 1 1 100.00
shadow_reg_update_error_with_csr_rw 1 1 100.00
aes_shadow_reg_errors_with_csr_rw 4.000s 190.337us 1 1 100.00
tl_intg_err 2 2 100.00
aes_tl_intg_err 3.000s 191.069us 1 1 100.00
aes_sec_cm 5.000s 2678.338us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
aes_tl_intg_err 3.000s 191.069us 1 1 100.00
sec_cm_lc_escalate_en_intersig_mubi 1 1 100.00
aes_alert_reset 2.000s 112.300us 1 1 100.00
sec_cm_main_config_shadow 1 1 100.00
aes_shadow_reg_errors 2.000s 162.038us 1 1 100.00
sec_cm_gcm_config_shadow 1 1 100.00
aes_shadow_reg_errors 2.000s 162.038us 1 1 100.00
sec_cm_main_config_sparse 4 4 100.00
aes_smoke 3.000s 117.142us 1 1 100.00
aes_stress 1.000s 61.047us 1 1 100.00
aes_alert_reset 2.000s 112.300us 1 1 100.00
aes_core_fi 2.000s 105.038us 1 1 100.00
sec_cm_gcm_config_sparse 4 4 100.00
aes_gcm_save_restore 3.000s 367.020us 1 1 100.00
aes_config_error 2.000s 59.546us 1 1 100.00
aes_stress 1.000s 61.047us 1 1 100.00
aes_core_fi 2.000s 105.038us 1 1 100.00
sec_cm_aux_config_shadow 1 1 100.00
aes_shadow_reg_errors 2.000s 162.038us 1 1 100.00
sec_cm_aux_config_regwen 2 2 100.00
aes_readability 2.000s 108.667us 1 1 100.00
aes_stress 1.000s 61.047us 1 1 100.00
sec_cm_key_sideload 2 2 100.00
aes_stress 1.000s 61.047us 1 1 100.00
aes_sideload 2.000s 87.845us 1 1 100.00
sec_cm_key_sw_unreadable 1 1 100.00
aes_readability 2.000s 108.667us 1 1 100.00
sec_cm_data_reg_sw_unreadable 1 1 100.00
aes_readability 2.000s 108.667us 1 1 100.00
sec_cm_key_sec_wipe 1 1 100.00
aes_readability 2.000s 108.667us 1 1 100.00
sec_cm_iv_config_sec_wipe 1 1 100.00
aes_readability 2.000s 108.667us 1 1 100.00
sec_cm_data_reg_sec_wipe 1 1 100.00
aes_readability 2.000s 108.667us 1 1 100.00
sec_cm_data_reg_key_sca 1 1 100.00
aes_stress 1.000s 61.047us 1 1 100.00
sec_cm_key_masking 1 1 100.00
aes_stress 1.000s 61.047us 1 1 100.00
sec_cm_main_fsm_sparse 1 1 100.00
aes_fi 3.000s 134.487us 1 1 100.00
sec_cm_main_fsm_redun 4 4 100.00
aes_fi 3.000s 134.487us 1 1 100.00
aes_control_fi 3.000s 60.362us 1 1 100.00
aes_cipher_fi 1.000s 45.832us 1 1 100.00
aes_ctr_fi 2.000s 54.091us 1 1 100.00
sec_cm_cipher_fsm_sparse 1 1 100.00
aes_fi 3.000s 134.487us 1 1 100.00
sec_cm_cipher_fsm_redun 3 3 100.00
aes_fi 3.000s 134.487us 1 1 100.00
aes_control_fi 3.000s 60.362us 1 1 100.00
aes_cipher_fi 1.000s 45.832us 1 1 100.00
sec_cm_cipher_ctr_redun 1 1 100.00
aes_cipher_fi 1.000s 45.832us 1 1 100.00
sec_cm_ctr_fsm_sparse 1 1 100.00
aes_fi 3.000s 134.487us 1 1 100.00
sec_cm_ctr_fsm_redun 3 3 100.00
aes_fi 3.000s 134.487us 1 1 100.00
aes_control_fi 3.000s 60.362us 1 1 100.00
aes_ctr_fi 2.000s 54.091us 1 1 100.00
sec_cm_ghash_fsm_sparse 1 1 100.00
aes_fi 3.000s 134.487us 1 1 100.00
sec_cm_ctrl_sparse 4 4 100.00
aes_fi 3.000s 134.487us 1 1 100.00
aes_control_fi 3.000s 60.362us 1 1 100.00
aes_cipher_fi 1.000s 45.832us 1 1 100.00
aes_ctr_fi 2.000s 54.091us 1 1 100.00
sec_cm_main_fsm_global_esc 1 1 100.00
aes_alert_reset 2.000s 112.300us 1 1 100.00
sec_cm_main_fsm_local_esc 4 4 100.00
aes_fi 3.000s 134.487us 1 1 100.00
aes_control_fi 3.000s 60.362us 1 1 100.00
aes_cipher_fi 1.000s 45.832us 1 1 100.00
aes_ctr_fi 2.000s 54.091us 1 1 100.00
sec_cm_cipher_fsm_local_esc 4 4 100.00
aes_fi 3.000s 134.487us 1 1 100.00
aes_control_fi 3.000s 60.362us 1 1 100.00
aes_cipher_fi 1.000s 45.832us 1 1 100.00
aes_ctr_fi 2.000s 54.091us 1 1 100.00
sec_cm_ctr_fsm_local_esc 3 3 100.00
aes_fi 3.000s 134.487us 1 1 100.00
aes_control_fi 3.000s 60.362us 1 1 100.00
aes_ctr_fi 2.000s 54.091us 1 1 100.00
sec_cm_ghash_fsm_local_esc 2 2 100.00
aes_fi 3.000s 134.487us 1 1 100.00
aes_ghash_fi 3.000s 92.148us 1 1 100.00
sec_cm_data_reg_local_esc 3 3 100.00
aes_fi 3.000s 134.487us 1 1 100.00
aes_control_fi 3.000s 60.362us 1 1 100.00
aes_cipher_fi 1.000s 45.832us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 0 1 0.00
aes_stress_all_with_rand_reset 4.000s 684.444us 0 1 0.00

Error Messages

   Test seed line log context
xmsim: *E,ASRTST (/nightly/current_run/scratch/master/aes_unmasked-sim-xcelium/default/fusesoc-work/src/lowrisc_ip_aes_*/rtl/aes_core.sv,1112): Assertion AesModeValid has failed
aes_stress_all_with_rand_reset 96146368869575190540713314371817274746638734074512630749293586049180851595661 500
xmsim: *E,ASRTST (/nightly/current_run/scratch/master/aes_unmasked-sim-xcelium/default/fusesoc-work/src/lowrisc_ip_aes_1.0/rtl/aes_core.sv,1112): (time 684443623 PS) Assertion tb.dut.u_aes_core.AesModeValid has failed
xmsim: *E,ASRTST (/nightly/current_run/scratch/master/aes_unmasked-sim-xcelium/default/fusesoc-work/src/lowrisc_ip_aes_1.0/rtl/aes_control_fsm.sv,1180): (time 684443623 PS) Assertion tb.dut.u_aes_core.u_aes_control.gen_fsm[2].gen_fsm_n.u_aes_control_fsm_i.u_aes_control_fsm.AesModeValid has failed
xmsim: *E,ASRTST (/nightly/current_run/scratch/master/aes_unmasked-sim-xcelium/default/fusesoc-work/src/lowrisc_ip_aes_1.0/rtl/aes_control_fsm.sv,1180): (time 684443623 PS) Assertion tb.dut.u_aes_core.u_aes_control.gen_fsm[1].gen_fsm_p.u_aes_control_fsm_i.u_aes_control_fsm.AesModeValid has failed
xmsim: *E,ASRTST (/nightly/current_run/scratch/master/aes_unmasked-sim-xcelium/default/fusesoc-work/src/lowrisc_ip_aes_1.0/rtl/aes_control_fsm.sv,1180): (time 684443623 PS) Assertion tb.dut.u_aes_core.u_aes_control.gen_fsm[0].gen_fsm_p.u_aes_control_fsm_i.u_aes_control_fsm.AesModeValid has failed
UVM_ERROR @ 684443623 ps: (aes_core.sv:1112) [ASSERT FAILED] AesModeValid