Simulation Results: alert_handler

 
07/04/2026 16:08:41 DVSim: v1.17.3 sha: ae672c6 json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 77.59 %
  • code
  • 84.60 %
  • assert
  • 96.84 %
  • func
  • 51.33 %
  • block
  • 98.09 %
  • line
  • 99.24 %
  • branch
  • 96.29 %
  • toggle
  • 79.72 %
  • FSM
  • 63.16 %
Validation stages
V1
100.00%
V2
78.95%
V2S
100.00%
V3
0.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
alert_handler_smoke 50.000s 581.971us 1 1 100.00
csr_hw_reset 1 1 100.00
alert_handler_csr_hw_reset 13.000s 133.122us 1 1 100.00
csr_rw 1 1 100.00
alert_handler_csr_rw 14.000s 105.637us 1 1 100.00
csr_bit_bash 1 1 100.00
alert_handler_csr_bit_bash 749.000s 40323.012us 1 1 100.00
csr_aliasing 1 1 100.00
alert_handler_csr_aliasing 164.000s 2088.487us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
alert_handler_csr_mem_rw_with_rand_reset 20.000s 330.305us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
alert_handler_csr_rw 14.000s 105.637us 1 1 100.00
alert_handler_csr_aliasing 164.000s 2088.487us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
esc_accum 1 1 100.00
alert_handler_esc_alert_accum 108.000s 1548.871us 1 1 100.00
esc_timeout 1 1 100.00
alert_handler_esc_intr_timeout 74.000s 1732.772us 1 1 100.00
entropy 1 1 100.00
alert_handler_entropy 3508.000s 40741.818us 1 1 100.00
sig_int_fail 1 1 100.00
alert_handler_sig_int_fail 50.000s 2002.559us 1 1 100.00
clk_skew 1 1 100.00
alert_handler_smoke 50.000s 581.971us 1 1 100.00
random_alerts 1 1 100.00
alert_handler_random_alerts 63.000s 692.677us 1 1 100.00
random_classes 1 1 100.00
alert_handler_random_classes 45.000s 732.484us 1 1 100.00
ping_timeout 0 1 0.00
alert_handler_ping_timeout 169.000s 38247.650us 0 1 0.00
lpg 1 2 50.00
alert_handler_lpg 1878.000s 49240.535us 1 1 100.00
alert_handler_lpg_stub_clk 0.000s 0.000us 0 1 0.00
stress_all 0 1 0.00
alert_handler_stress_all 2383.000s 89384.944us 0 1 0.00
alert_handler_entropy_stress_test 1 1 100.00
alert_handler_entropy_stress 8.000s 1415.905us 1 1 100.00
alert_handler_alert_accum_saturation 0 1 0.00
alert_handler_alert_accum_saturation 2.000s 0.000us 0 1 0.00
intr_test 1 1 100.00
alert_handler_intr_test 3.000s 15.781us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
alert_handler_tl_errors 14.000s 288.368us 1 1 100.00
tl_d_illegal_access 1 1 100.00
alert_handler_tl_errors 14.000s 288.368us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
alert_handler_csr_hw_reset 13.000s 133.122us 1 1 100.00
alert_handler_csr_rw 14.000s 105.637us 1 1 100.00
alert_handler_csr_aliasing 164.000s 2088.487us 1 1 100.00
alert_handler_same_csr_outstanding 33.000s 196.140us 1 1 100.00
tl_d_partial_access 4 4 100.00
alert_handler_csr_hw_reset 13.000s 133.122us 1 1 100.00
alert_handler_csr_rw 14.000s 105.637us 1 1 100.00
alert_handler_csr_aliasing 164.000s 2088.487us 1 1 100.00
alert_handler_same_csr_outstanding 33.000s 196.140us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
shadow_reg_update_error 1 1 100.00
alert_handler_shadow_reg_errors 111.000s 1789.776us 1 1 100.00
shadow_reg_read_clear_staged_value 1 1 100.00
alert_handler_shadow_reg_errors 111.000s 1789.776us 1 1 100.00
shadow_reg_storage_error 1 1 100.00
alert_handler_shadow_reg_errors 111.000s 1789.776us 1 1 100.00
shadowed_reset_glitch 1 1 100.00
alert_handler_shadow_reg_errors 111.000s 1789.776us 1 1 100.00
shadow_reg_update_error_with_csr_rw 1 1 100.00
alert_handler_shadow_reg_errors_with_csr_rw 829.000s 19541.356us 1 1 100.00
tl_intg_err 2 2 100.00
alert_handler_sec_cm 19.000s 344.125us 1 1 100.00
alert_handler_tl_intg_err 5.000s 26.937us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
alert_handler_tl_intg_err 5.000s 26.937us 1 1 100.00
sec_cm_config_shadow 1 1 100.00
alert_handler_shadow_reg_errors 111.000s 1789.776us 1 1 100.00
sec_cm_ping_timer_config_regwen 1 1 100.00
alert_handler_smoke 50.000s 581.971us 1 1 100.00
sec_cm_alert_config_regwen 1 1 100.00
alert_handler_smoke 50.000s 581.971us 1 1 100.00
sec_cm_alert_loc_config_regwen 1 1 100.00
alert_handler_smoke 50.000s 581.971us 1 1 100.00
sec_cm_class_config_regwen 1 1 100.00
alert_handler_smoke 50.000s 581.971us 1 1 100.00
sec_cm_alert_intersig_diff 1 1 100.00
alert_handler_sig_int_fail 50.000s 2002.559us 1 1 100.00
sec_cm_lpg_intersig_mubi 1 1 100.00
alert_handler_lpg 1878.000s 49240.535us 1 1 100.00
sec_cm_esc_intersig_diff 1 1 100.00
alert_handler_sig_int_fail 50.000s 2002.559us 1 1 100.00
sec_cm_alert_rx_intersig_bkgn_chk 1 1 100.00
alert_handler_entropy 3508.000s 40741.818us 1 1 100.00
sec_cm_esc_tx_intersig_bkgn_chk 1 1 100.00
alert_handler_entropy 3508.000s 40741.818us 1 1 100.00
sec_cm_esc_timer_fsm_sparse 1 1 100.00
alert_handler_sec_cm 19.000s 344.125us 1 1 100.00
sec_cm_ping_timer_fsm_sparse 1 1 100.00
alert_handler_sec_cm 19.000s 344.125us 1 1 100.00
sec_cm_esc_timer_fsm_local_esc 1 1 100.00
alert_handler_sec_cm 19.000s 344.125us 1 1 100.00
sec_cm_ping_timer_fsm_local_esc 1 1 100.00
alert_handler_sec_cm 19.000s 344.125us 1 1 100.00
sec_cm_esc_timer_fsm_global_esc 1 1 100.00
alert_handler_sec_cm 19.000s 344.125us 1 1 100.00
sec_cm_accu_ctr_redun 1 1 100.00
alert_handler_sec_cm 19.000s 344.125us 1 1 100.00
sec_cm_esc_timer_ctr_redun 1 1 100.00
alert_handler_sec_cm 19.000s 344.125us 1 1 100.00
sec_cm_ping_timer_ctr_redun 1 1 100.00
alert_handler_sec_cm 19.000s 344.125us 1 1 100.00
sec_cm_ping_timer_lfsr_redun 1 1 100.00
alert_handler_sec_cm 19.000s 344.125us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 0 1 0.00
alert_handler_stress_all_with_rand_reset 83.000s 1869.997us 0 1 0.00

Error Messages

   Test seed line log context
UVM_ERROR (alert_handler_scoreboard.sv:486) [scoreboard] Check failed intr_state_val == item.d_data (* [*] vs * [*]) reg name: intr_state
alert_handler_ping_timeout 83799802178996615418161807166697841959681566850960302382999848764734130985242 102
UVM_ERROR @ 38247649695 ps: (alert_handler_scoreboard.sv:486) [uvm_test_top.env.scoreboard] Check failed intr_state_val == item.d_data (0 [0x0] vs 2 [0x2]) reg name: intr_state
UVM_INFO @ 38247649695 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Job timed out after * minutes
alert_handler_lpg_stub_clk 63602215337640300479717541577932764534482992981017326325265994112207874680576 None
Job timed out after 60 minutes
UVM_ERROR (alert_handler_scoreboard.sv:491) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) reg name: alert_handler_reg_block.classb_state
alert_handler_stress_all 34720637651180046461636999671439956681270075593212063787460084536411228887733 174
UVM_ERROR @ 89384943558 ps: (alert_handler_scoreboard.sv:491) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 4 [0x4]) reg name: alert_handler_reg_block.classb_state
UVM_INFO @ 89384943558 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (uvm_hdl_inca.c:743) [UVM/DPI/NOBJ3] name tb.dut.gen_classes[``i``].u_accu.u_prim_count.cnt_q[*] cannot be resolved to a hdl object (vlog,vhdl,vlog-slice)
alert_handler_alert_accum_saturation 66216484244609363156184708253025867067426232032508648445379516740339502811438 88
UVM_ERROR @ 0 ps: (uvm_hdl_inca.c:743) [UVM/DPI/NOBJ3] name tb.dut.gen_classes[``i``].u_accu.u_prim_count.cnt_q[0] cannot be resolved to a hdl object (vlog,vhdl,vlog-slice)
UVM_INFO @ 0 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (alert_handler_scoreboard.sv:491) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) reg name: alert_handler_reg_block.classa_state
alert_handler_stress_all_with_rand_reset 112068315879289201501677139050158112978812917003075913258130281913625647627829 118
UVM_ERROR @ 1869996819 ps: (alert_handler_scoreboard.sv:491) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 3 [0x3]) reg name: alert_handler_reg_block.classa_state
UVM_INFO @ 1869996819 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---