| V1 |
|
18.18% |
| V2 |
|
26.13% |
| V2S |
|
100.00% |
| V3 |
|
0.00% |
| unmapped |
|
40.00% |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| chip_sw_uart_tx_rx | 0 | 1 | 0.00 | |||
| chip_sw_uart_tx_rx | 117.083s | 0.000us | 0 | 1 | 0.00 | |
| chip_sw_uart_rx_overflow | 0 | 1 | 0.00 | |||
| chip_sw_uart_tx_rx | 117.083s | 0.000us | 0 | 1 | 0.00 | |
| chip_sw_uart_rand_baudrate | 0 | 1 | 0.00 | |||
| chip_sw_uart_rand_baudrate | 90.010s | 0.000us | 0 | 1 | 0.00 | |
| chip_sw_uart_tx_rx_alt_clk_freq | 0 | 1 | 0.00 | |||
| chip_sw_uart_tx_rx_alt_clk_freq | 56.045s | 0.000us | 0 | 1 | 0.00 | |
| chip_sw_gpio_out | 1 | 1 | 100.00 | |||
| chip_sw_gpio | 1774.000s | 289.415us | 1 | 1 | 100.00 | |
| chip_sw_gpio_in | 1 | 1 | 100.00 | |||
| chip_sw_gpio | 1774.000s | 289.415us | 1 | 1 | 100.00 | |
| chip_sw_gpio_irq | 1 | 1 | 100.00 | |||
| chip_sw_gpio | 1774.000s | 289.415us | 1 | 1 | 100.00 | |
| chip_sw_example_tests | 1 | 4 | 25.00 | |||
| chip_sw_example_rom | 22.000s | 10.380us | 0 | 1 | 0.00 | |
| chip_sw_example_manufacturer | 130.749s | 0.000us | 0 | 1 | 0.00 | |
| chip_sw_example_concurrency | 923.000s | 169.399us | 1 | 1 | 100.00 | |
| chip_sw_uart_smoketest_signed | 8.301s | 0.000us | 0 | 1 | 0.00 | |
| csr_bit_bash | 0 | 1 | 0.00 | |||
| chip_csr_bit_bash | 16.000s | 0.000us | 0 | 1 | 0.00 | |
| csr_aliasing | 0 | 1 | 0.00 | |||
| chip_csr_aliasing | 16.000s | 0.000us | 0 | 1 | 0.00 | |
| regwen_csr_and_corresponding_lockable_csr | 0 | 1 | 0.00 | |||
| chip_csr_aliasing | 16.000s | 0.000us | 0 | 1 | 0.00 | |
| xbar_smoke | 0 | 1 | 0.00 | |||
| xbar_smoke | 57.000s | 64.287us | 0 | 1 | 0.00 | |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| chip_sw_spi_device_flash_mode | 0 | 1 | 0.00 | |||
| chip_sw_uart_tx_rx_bootstrap | 100.225s | 0.000us | 0 | 1 | 0.00 | |
| chip_sw_spi_device_pass_through | 0 | 1 | 0.00 | |||
| chip_sw_spi_device_pass_through | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| chip_sw_spi_device_pass_through_collision | 0 | 1 | 0.00 | |||
| chip_sw_spi_device_pass_through_collision | 1765.000s | 306.663us | 0 | 1 | 0.00 | |
| chip_sw_spi_device_tpm | 0 | 1 | 0.00 | |||
| chip_sw_spi_device_tpm | 24.734s | 0.000us | 0 | 1 | 0.00 | |
| chip_sw_spi_host_tx_rx | 0 | 1 | 0.00 | |||
| chip_sw_spi_host_tx_rx | 15.095s | 0.000us | 0 | 1 | 0.00 | |
| chip_sw_i2c_host_tx_rx | 0 | 1 | 0.00 | |||
| chip_sw_i2c_host_tx_rx | 38.152s | 0.000us | 0 | 1 | 0.00 | |
| chip_sw_i2c_device_tx_rx | 0 | 1 | 0.00 | |||
| chip_sw_i2c_device_tx_rx | 25.988s | 0.000us | 0 | 1 | 0.00 | |
| chip_pin_mux | 0 | 1 | 0.00 | |||
| chip_padctrl_attributes | 15.000s | 0.000us | 0 | 1 | 0.00 | |
| chip_padctrl_attributes | 0 | 1 | 0.00 | |||
| chip_padctrl_attributes | 15.000s | 0.000us | 0 | 1 | 0.00 | |
| chip_sw_sleep_pin_wake | 0 | 1 | 0.00 | |||
| chip_sw_sleep_pin_wake | 127.290s | 0.000us | 0 | 1 | 0.00 | |
| chip_sw_sleep_pin_retention | 0 | 1 | 0.00 | |||
| chip_sw_sleep_pin_retention | 140.513s | 0.000us | 0 | 1 | 0.00 | |
| chip_sw_data_integrity | 0 | 1 | 0.00 | |||
| chip_sw_data_integrity_escalation | 168.807s | 0.000us | 0 | 1 | 0.00 | |
| chip_sw_instruction_integrity | 0 | 1 | 0.00 | |||
| chip_sw_data_integrity_escalation | 168.807s | 0.000us | 0 | 1 | 0.00 | |
| chip_jtag_csr_rw | 0 | 1 | 0.00 | |||
| chip_jtag_csr_rw | 656.000s | 117.028us | 0 | 1 | 0.00 | |
| chip_jtag_mem_access | 0 | 1 | 0.00 | |||
| chip_jtag_mem_access | 670.000s | 117.031us | 0 | 1 | 0.00 | |
| chip_rv_dm_ndm_reset_req | 1 | 1 | 100.00 | |||
| chip_rv_dm_ndm_reset_req | 1712.000s | 310.834us | 1 | 1 | 100.00 | |
| chip_sw_rv_dm_ndm_reset_req_when_cpu_halted | 0 | 1 | 0.00 | |||
| chip_sw_rv_dm_ndm_reset_req_when_cpu_halted | 8.605s | 0.000us | 0 | 1 | 0.00 | |
| chip_rv_dm_access_after_wakeup | 0 | 1 | 0.00 | |||
| chip_sw_rv_dm_access_after_wakeup | 7.741s | 0.000us | 0 | 1 | 0.00 | |
| chip_rv_dm_lc_disabled | 0 | 1 | 0.00 | |||
| chip_rv_dm_lc_disabled | 961.000s | 379.420us | 0 | 1 | 0.00 | |
| chip_sw_timer | 1 | 1 | 100.00 | |||
| chip_sw_rv_timer_irq | 1509.000s | 267.610us | 1 | 1 | 100.00 | |
| chip_sw_aon_timer_wakeup_irq | 0 | 1 | 0.00 | |||
| chip_sw_aon_timer_irq | 3016.000s | 520.510us | 0 | 1 | 0.00 | |
| chip_sw_aon_timer_wdog_bark_irq | 0 | 1 | 0.00 | |||
| chip_sw_aon_timer_irq | 3016.000s | 520.510us | 0 | 1 | 0.00 | |
| chip_sw_aon_timer_wdog_lc_escalate | 1 | 1 | 100.00 | |||
| chip_sw_aon_timer_wdog_lc_escalate | 2422.000s | 390.930us | 1 | 1 | 100.00 | |
| chip_sw_aon_timer_wdog_bite_reset | 0 | 1 | 0.00 | |||
| chip_sw_aon_timer_wdog_bite_reset | 1120.000s | 183.224us | 0 | 1 | 0.00 | |
| chip_sw_aon_timer_sleep_wdog_bite_reset | 0 | 1 | 0.00 | |||
| chip_sw_aon_timer_wdog_bite_reset | 1120.000s | 183.224us | 0 | 1 | 0.00 | |
| chip_sw_aon_timer_sleep_wdog_sleep_pause | 1 | 1 | 100.00 | |||
| chip_sw_aon_timer_sleep_wdog_sleep_pause | 1895.000s | 2309.410us | 1 | 1 | 100.00 | |
| chip_sw_plic_sw_irq | 1 | 1 | 100.00 | |||
| chip_sw_plic_sw_irq | 1069.000s | 164.393us | 1 | 1 | 100.00 | |
| chip_sw_clkmgr_idle_trans | 4 | 4 | 100.00 | |||
| chip_sw_otbn_randomness | 1536.000s | 244.620us | 1 | 1 | 100.00 | |
| chip_sw_aes_idle | 1011.000s | 165.371us | 1 | 1 | 100.00 | |
| chip_sw_hmac_enc_idle | 1152.000s | 180.065us | 1 | 1 | 100.00 | |
| chip_sw_kmac_idle | 1046.000s | 163.864us | 1 | 1 | 100.00 | |
| chip_sw_clkmgr_off_trans | 0 | 4 | 0.00 | |||
| chip_sw_clkmgr_off_aes_trans | 1147.000s | 184.552us | 0 | 1 | 0.00 | |
| chip_sw_clkmgr_off_hmac_trans | 1207.000s | 184.648us | 0 | 1 | 0.00 | |
| chip_sw_clkmgr_off_kmac_trans | 1162.000s | 184.520us | 0 | 1 | 0.00 | |
| chip_sw_clkmgr_off_otbn_trans | 1133.000s | 184.536us | 0 | 1 | 0.00 | |
| chip_sw_clkmgr_jitter | 1 | 7 | 14.29 | |||
| chip_sw_otbn_ecdsa_op_irq_jitter_en | 21.000s | 10.260us | 0 | 1 | 0.00 | |
| chip_sw_aes_enc_jitter_en | 30.000s | 10.380us | 0 | 1 | 0.00 | |
| chip_sw_hmac_enc_jitter_en | 25.000s | 10.380us | 0 | 1 | 0.00 | |
| chip_sw_keymgr_dpe_key_derivation_jitter_en | 30.000s | 10.380us | 0 | 1 | 0.00 | |
| chip_sw_kmac_mode_kmac_jitter_en | 22.000s | 10.100us | 0 | 1 | 0.00 | |
| chip_sw_sram_ctrl_scrambled_access_jitter_en | 10.772s | 0.000us | 0 | 1 | 0.00 | |
| chip_sw_clkmgr_jitter | 1051.000s | 160.929us | 1 | 1 | 100.00 | |
| chip_sw_clkmgr_extended_range | 1 | 8 | 12.50 | |||
| chip_sw_clkmgr_jitter_reduced_freq | 1935.000s | 1964.554us | 1 | 1 | 100.00 | |
| chip_sw_otbn_ecdsa_op_irq_jitter_en_reduced_freq | 26.000s | 10.240us | 0 | 1 | 0.00 | |
| chip_sw_aes_enc_jitter_en_reduced_freq | 22.000s | 10.400us | 0 | 1 | 0.00 | |
| chip_sw_hmac_enc_jitter_en_reduced_freq | 27.000s | 10.380us | 0 | 1 | 0.00 | |
| chip_sw_keymgr_dpe_key_derivation_jitter_en_reduced_freq | 24.000s | 10.340us | 0 | 1 | 0.00 | |
| chip_sw_kmac_mode_kmac_jitter_en_reduced_freq | 22.000s | 10.400us | 0 | 1 | 0.00 | |
| chip_sw_sram_ctrl_scrambled_access_jitter_en_reduced_freq | 27.000s | 10.180us | 0 | 1 | 0.00 | |
| chip_sw_csrng_edn_concurrency_reduced_freq | 28.000s | 10.100us | 0 | 1 | 0.00 | |
| chip_sw_clkmgr_deep_sleep_frequency | 0 | 1 | 0.00 | |||
| chip_sw_ast_clk_outputs | 8.761s | 0.000us | 0 | 1 | 0.00 | |
| chip_sw_clkmgr_sleep_frequency | 0 | 1 | 0.00 | |||
| chip_sw_clkmgr_sleep_frequency | 11.101s | 0.000us | 0 | 1 | 0.00 | |
| chip_sw_clkmgr_reset_frequency | 0 | 1 | 0.00 | |||
| chip_sw_clkmgr_reset_frequency | 8.530s | 0.000us | 0 | 1 | 0.00 | |
| chip_sw_clkmgr_escalation_reset | 0 | 1 | 0.00 | |||
| chip_sw_all_escalation_resets | 1035.000s | 180.078us | 0 | 1 | 0.00 | |
| chip_sw_pwrmgr_external_full_reset | 1 | 1 | 100.00 | |||
| chip_sw_pwrmgr_full_aon_reset | 2460.000s | 505.173us | 1 | 1 | 100.00 | |
| chip_sw_pwrmgr_sleep_all_reset_reqs | 0 | 1 | 0.00 | |||
| chip_sw_aon_timer_wdog_bite_reset | 1120.000s | 183.224us | 0 | 1 | 0.00 | |
| chip_sw_pwrmgr_wdog_reset | 0 | 1 | 0.00 | |||
| chip_sw_pwrmgr_wdog_reset | 12.036s | 0.000us | 0 | 1 | 0.00 | |
| chip_sw_pwrmgr_aon_power_glitch_reset | 1 | 1 | 100.00 | |||
| chip_sw_pwrmgr_full_aon_reset | 2460.000s | 505.173us | 1 | 1 | 100.00 | |
| chip_sw_pwrmgr_main_power_glitch_reset | 0 | 1 | 0.00 | |||
| chip_sw_pwrmgr_main_power_glitch_reset | 10.989s | 0.000us | 0 | 1 | 0.00 | |
| chip_sw_pwrmgr_random_sleep_power_glitch_reset | 0 | 1 | 0.00 | |||
| chip_sw_pwrmgr_random_sleep_power_glitch_reset | 9.834s | 0.000us | 0 | 1 | 0.00 | |
| chip_sw_pwrmgr_deep_sleep_power_glitch_reset | 0 | 1 | 0.00 | |||
| chip_sw_pwrmgr_deep_sleep_power_glitch_reset | 9.729s | 0.000us | 0 | 1 | 0.00 | |
| chip_sw_pwrmgr_sleep_power_glitch_reset | 0 | 1 | 0.00 | |||
| chip_sw_pwrmgr_sleep_power_glitch_reset | 8.893s | 0.000us | 0 | 1 | 0.00 | |
| chip_sw_pwrmgr_sleep_disabled | 0 | 1 | 0.00 | |||
| chip_sw_pwrmgr_sleep_disabled | 10.011s | 0.000us | 0 | 1 | 0.00 | |
| chip_sw_pwrmgr_escalation_reset | 0 | 1 | 0.00 | |||
| chip_sw_all_escalation_resets | 1035.000s | 180.078us | 0 | 1 | 0.00 | |
| chip_sw_rstmgr_sys_reset_info | 1 | 1 | 100.00 | |||
| chip_rv_dm_ndm_reset_req | 1712.000s | 310.834us | 1 | 1 | 100.00 | |
| chip_sw_rstmgr_cpu_info | 0 | 1 | 0.00 | |||
| chip_sw_rstmgr_cpu_info | 2590.000s | 413.096us | 0 | 1 | 0.00 | |
| chip_sw_rstmgr_sw_req_reset | 1 | 1 | 100.00 | |||
| chip_sw_rstmgr_sw_req | 1862.000s | 305.315us | 1 | 1 | 100.00 | |
| chip_sw_rstmgr_alert_info | 0 | 1 | 0.00 | |||
| chip_sw_rstmgr_alert_info | 2142.000s | 334.791us | 0 | 1 | 0.00 | |
| chip_sw_rstmgr_sw_rst | 1 | 1 | 100.00 | |||
| chip_sw_rstmgr_sw_rst | 875.000s | 163.195us | 1 | 1 | 100.00 | |
| chip_sw_rstmgr_escalation_reset | 0 | 1 | 0.00 | |||
| chip_sw_all_escalation_resets | 1035.000s | 180.078us | 0 | 1 | 0.00 | |
| chip_sw_alert_handler_alerts | 0 | 1 | 0.00 | |||
| chip_sw_alert_test | 7.565s | 0.000us | 0 | 1 | 0.00 | |
| chip_sw_alert_handler_escalations | 0 | 1 | 0.00 | |||
| chip_sw_alert_handler_escalation | 8.389s | 0.000us | 0 | 1 | 0.00 | |
| chip_sw_all_escalation_resets | 0 | 1 | 0.00 | |||
| chip_sw_all_escalation_resets | 1035.000s | 180.078us | 0 | 1 | 0.00 | |
| chip_sw_alert_handler_entropy | 0 | 1 | 0.00 | |||
| chip_sw_alert_handler_entropy | 11.398s | 0.000us | 0 | 1 | 0.00 | |
| chip_sw_alert_handler_crashdump | 0 | 1 | 0.00 | |||
| chip_sw_rstmgr_alert_info | 2142.000s | 334.791us | 0 | 1 | 0.00 | |
| chip_sw_alert_handler_ping_timeout | 1 | 1 | 100.00 | |||
| chip_sw_alert_handler_ping_timeout | 2342.000s | 404.959us | 1 | 1 | 100.00 | |
| chip_sw_alert_handler_lpg_sleep_mode_alerts | 0 | 1 | 0.00 | |||
| chip_sw_alert_handler_lpg_sleep_mode_alerts | 7.844s | 0.000us | 0 | 1 | 0.00 | |
| chip_sw_alert_handler_lpg_sleep_mode_pings | 0 | 1 | 0.00 | |||
| chip_sw_alert_handler_lpg_sleep_mode_pings | 8.549s | 0.000us | 0 | 1 | 0.00 | |
| chip_sw_alert_handler_lpg_clock_off | 0 | 1 | 0.00 | |||
| chip_sw_alert_handler_lpg_clkoff | 8.888s | 0.000us | 0 | 1 | 0.00 | |
| chip_sw_alert_handler_lpg_reset_toggle | 0 | 1 | 0.00 | |||
| chip_sw_alert_handler_lpg_reset_toggle | 8.849s | 0.000us | 0 | 1 | 0.00 | |
| chip_sw_alert_handler_reverse_ping_in_deep_sleep | 0 | 1 | 0.00 | |||
| chip_sw_alert_handler_reverse_ping_in_deep_sleep | 11.146s | 0.000us | 0 | 1 | 0.00 | |
| chip_sw_lc_ctrl_alert_handler_escalation | 0 | 1 | 0.00 | |||
| chip_sw_alert_handler_escalation | 8.389s | 0.000us | 0 | 1 | 0.00 | |
| chip_sw_lc_ctrl_jtag_access | 0 | 1 | 0.00 | |||
| chip_sw_lc_ctrl_transition | 17.129s | 0.000us | 0 | 1 | 0.00 | |
| chip_sw_lc_ctrl_otp_hw_cfg | 0 | 1 | 0.00 | |||
| chip_sw_lc_ctrl_otp_hw_cfg | 8.902s | 0.000us | 0 | 1 | 0.00 | |
| chip_sw_lc_ctrl_init | 0 | 1 | 0.00 | |||
| chip_sw_lc_ctrl_transition | 17.129s | 0.000us | 0 | 1 | 0.00 | |
| chip_sw_lc_ctrl_transitions | 0 | 1 | 0.00 | |||
| chip_sw_lc_ctrl_transition | 17.129s | 0.000us | 0 | 1 | 0.00 | |
| chip_sw_lc_ctrl_kmac_req | 0 | 1 | 0.00 | |||
| chip_sw_lc_ctrl_transition | 17.129s | 0.000us | 0 | 1 | 0.00 | |
| chip_sw_lc_ctrl_key_div | 0 | 1 | 0.00 | |||
| chip_sw_keymgr_dpe_key_derivation_prod | 1964.000s | 305.219us | 0 | 1 | 0.00 | |
| chip_sw_lc_ctrl_broadcast | 1 | 10 | 10.00 | |||
| chip_prim_tl_access | 2839.000s | 974.891us | 1 | 1 | 100.00 | |
| chip_rv_dm_lc_disabled | 961.000s | 379.420us | 0 | 1 | 0.00 | |
| chip_sw_otp_ctrl_lc_signals_test_unlocked0 | 18.125s | 0.000us | 0 | 1 | 0.00 | |
| chip_sw_otp_ctrl_lc_signals_dev | 40.796s | 0.000us | 0 | 1 | 0.00 | |
| chip_sw_otp_ctrl_lc_signals_prod | 19.415s | 0.000us | 0 | 1 | 0.00 | |
| chip_sw_otp_ctrl_lc_signals_rma | 11.464s | 0.000us | 0 | 1 | 0.00 | |
| chip_sw_lc_ctrl_transition | 17.129s | 0.000us | 0 | 1 | 0.00 | |
| chip_sw_keymgr_dpe_key_derivation | 1953.000s | 305.033us | 0 | 1 | 0.00 | |
| chip_sw_rom_ctrl_integrity_check | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| chip_sw_sram_ctrl_execution_main | 11.184s | 0.000us | 0 | 1 | 0.00 | |
| chip_sw_aes_enc | 1 | 2 | 50.00 | |||
| chip_sw_aes_enc | 1082.000s | 175.417us | 1 | 1 | 100.00 | |
| chip_sw_aes_enc_jitter_en | 30.000s | 10.380us | 0 | 1 | 0.00 | |
| chip_sw_aes_gcm | 1 | 2 | 50.00 | |||
| chip_sw_aes_enc | 1082.000s | 175.417us | 1 | 1 | 100.00 | |
| chip_sw_aes_enc_jitter_en | 30.000s | 10.380us | 0 | 1 | 0.00 | |
| chip_sw_aes_entropy | 1 | 1 | 100.00 | |||
| chip_sw_aes_entropy | 1029.000s | 164.743us | 1 | 1 | 100.00 | |
| chip_sw_aes_idle | 1 | 1 | 100.00 | |||
| chip_sw_aes_idle | 1011.000s | 165.371us | 1 | 1 | 100.00 | |
| chip_sw_hmac_enc | 1 | 2 | 50.00 | |||
| chip_sw_hmac_enc | 1098.000s | 175.389us | 1 | 1 | 100.00 | |
| chip_sw_hmac_enc_jitter_en | 25.000s | 10.380us | 0 | 1 | 0.00 | |
| chip_sw_hmac_idle | 1 | 1 | 100.00 | |||
| chip_sw_hmac_enc_idle | 1152.000s | 180.065us | 1 | 1 | 100.00 | |
| chip_sw_kmac_enc | 2 | 3 | 66.67 | |||
| chip_sw_kmac_mode_cshake | 1051.000s | 167.822us | 1 | 1 | 100.00 | |
| chip_sw_kmac_mode_kmac | 1224.000s | 191.689us | 1 | 1 | 100.00 | |
| chip_sw_kmac_mode_kmac_jitter_en | 22.000s | 10.100us | 0 | 1 | 0.00 | |
| chip_sw_kmac_app_keymgr | 0 | 1 | 0.00 | |||
| chip_sw_keymgr_dpe_key_derivation | 1953.000s | 305.033us | 0 | 1 | 0.00 | |
| chip_sw_kmac_app_lc | 0 | 1 | 0.00 | |||
| chip_sw_lc_ctrl_transition | 17.129s | 0.000us | 0 | 1 | 0.00 | |
| chip_sw_kmac_app_rom | 0 | 1 | 0.00 | |||
| chip_sw_kmac_app_rom | 12.395s | 0.000us | 0 | 1 | 0.00 | |
| chip_sw_kmac_entropy | 1 | 1 | 100.00 | |||
| chip_sw_kmac_entropy | 1462.000s | 235.826us | 1 | 1 | 100.00 | |
| chip_sw_kmac_idle | 1 | 1 | 100.00 | |||
| chip_sw_kmac_idle | 1046.000s | 163.864us | 1 | 1 | 100.00 | |
| chip_sw_entropy_src_csrng | 1 | 1 | 100.00 | |||
| chip_sw_entropy_src_csrng | 1725.000s | 261.260us | 1 | 1 | 100.00 | |
| chip_sw_csrng_edn_cmd | 1 | 1 | 100.00 | |||
| chip_sw_entropy_src_csrng | 1725.000s | 261.260us | 1 | 1 | 100.00 | |
| chip_sw_csrng_fuse_en_sw_app_read | 0 | 1 | 0.00 | |||
| chip_sw_csrng_fuse_en_sw_app_read_test | 12.344s | 0.000us | 0 | 1 | 0.00 | |
| chip_sw_csrng_known_answer_tests | 1 | 1 | 100.00 | |||
| chip_sw_csrng_kat_test | 1137.000s | 175.946us | 1 | 1 | 100.00 | |
| chip_sw_edn_entropy_reqs | 1 | 1 | 100.00 | |||
| chip_sw_csrng_edn_concurrency | 4455.000s | 1010.650us | 1 | 1 | 100.00 | |
| chip_sw_keymgr_dpe_key_derivation | 0 | 2 | 0.00 | |||
| chip_sw_keymgr_dpe_key_derivation | 1953.000s | 305.033us | 0 | 1 | 0.00 | |
| chip_sw_keymgr_dpe_key_derivation_jitter_en | 30.000s | 10.380us | 0 | 1 | 0.00 | |
| chip_sw_otbn_op | 1 | 2 | 50.00 | |||
| chip_sw_otbn_ecdsa_op_irq | 6479.000s | 1495.104us | 1 | 1 | 100.00 | |
| chip_sw_otbn_ecdsa_op_irq_jitter_en | 21.000s | 10.260us | 0 | 1 | 0.00 | |
| chip_sw_otbn_rnd_entropy | 1 | 1 | 100.00 | |||
| chip_sw_otbn_randomness | 1536.000s | 244.620us | 1 | 1 | 100.00 | |
| chip_sw_otbn_urnd_entropy | 1 | 1 | 100.00 | |||
| chip_sw_otbn_randomness | 1536.000s | 244.620us | 1 | 1 | 100.00 | |
| chip_sw_otbn_idle | 1 | 1 | 100.00 | |||
| chip_sw_otbn_randomness | 1536.000s | 244.620us | 1 | 1 | 100.00 | |
| chip_sw_otbn_mem_scramble | 1 | 1 | 100.00 | |||
| chip_sw_otbn_mem_scramble | 1805.000s | 279.325us | 1 | 1 | 100.00 | |
| chip_sw_rom_access | 0 | 1 | 0.00 | |||
| chip_sw_rom_ctrl_integrity_check | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| chip_sw_rom_ctrl_integrity_check | 0 | 1 | 0.00 | |||
| chip_sw_rom_ctrl_integrity_check | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| chip_sw_sram_scrambled_access | 1 | 2 | 50.00 | |||
| chip_sw_sram_ctrl_scrambled_access | 2253.000s | 361.285us | 1 | 1 | 100.00 | |
| chip_sw_sram_ctrl_scrambled_access_jitter_en | 10.772s | 0.000us | 0 | 1 | 0.00 | |
| chip_sw_sram_execution | 0 | 1 | 0.00 | |||
| chip_sw_sram_ctrl_execution_main | 11.184s | 0.000us | 0 | 1 | 0.00 | |
| chip_sw_sram_lc_escalation | 0 | 2 | 0.00 | |||
| chip_sw_all_escalation_resets | 1035.000s | 180.078us | 0 | 1 | 0.00 | |
| chip_sw_data_integrity_escalation | 168.807s | 0.000us | 0 | 1 | 0.00 | |
| chip_otp_ctrl_init | 0 | 1 | 0.00 | |||
| chip_sw_lc_ctrl_transition | 17.129s | 0.000us | 0 | 1 | 0.00 | |
| chip_sw_otp_ctrl_keys | 3 | 4 | 75.00 | |||
| chip_sw_otbn_mem_scramble | 1805.000s | 279.325us | 1 | 1 | 100.00 | |
| chip_sw_keymgr_dpe_key_derivation | 1953.000s | 305.033us | 0 | 1 | 0.00 | |
| chip_sw_sram_ctrl_scrambled_access | 2253.000s | 361.285us | 1 | 1 | 100.00 | |
| chip_sw_rv_core_ibex_icache_invalidate | 1101.000s | 180.166us | 1 | 1 | 100.00 | |
| chip_sw_otp_ctrl_entropy | 3 | 4 | 75.00 | |||
| chip_sw_otbn_mem_scramble | 1805.000s | 279.325us | 1 | 1 | 100.00 | |
| chip_sw_keymgr_dpe_key_derivation | 1953.000s | 305.033us | 0 | 1 | 0.00 | |
| chip_sw_sram_ctrl_scrambled_access | 2253.000s | 361.285us | 1 | 1 | 100.00 | |
| chip_sw_rv_core_ibex_icache_invalidate | 1101.000s | 180.166us | 1 | 1 | 100.00 | |
| chip_sw_otp_ctrl_program | 0 | 1 | 0.00 | |||
| chip_sw_lc_ctrl_transition | 17.129s | 0.000us | 0 | 1 | 0.00 | |
| chip_sw_otp_ctrl_program_error | 0 | 1 | 0.00 | |||
| chip_sw_lc_ctrl_program_error | 10.215s | 0.000us | 0 | 1 | 0.00 | |
| chip_sw_otp_ctrl_hw_cfg | 0 | 1 | 0.00 | |||
| chip_sw_lc_ctrl_otp_hw_cfg | 8.902s | 0.000us | 0 | 1 | 0.00 | |
| chip_sw_otp_ctrl_lc_signals | 1 | 6 | 16.67 | |||
| chip_prim_tl_access | 2839.000s | 974.891us | 1 | 1 | 100.00 | |
| chip_sw_otp_ctrl_lc_signals_test_unlocked0 | 18.125s | 0.000us | 0 | 1 | 0.00 | |
| chip_sw_otp_ctrl_lc_signals_dev | 40.796s | 0.000us | 0 | 1 | 0.00 | |
| chip_sw_otp_ctrl_lc_signals_prod | 19.415s | 0.000us | 0 | 1 | 0.00 | |
| chip_sw_otp_ctrl_lc_signals_rma | 11.464s | 0.000us | 0 | 1 | 0.00 | |
| chip_sw_lc_ctrl_transition | 17.129s | 0.000us | 0 | 1 | 0.00 | |
| chip_sw_otp_prim_tl_access | 1 | 1 | 100.00 | |||
| chip_prim_tl_access | 2839.000s | 974.891us | 1 | 1 | 100.00 | |
| chip_sw_otp_ctrl_nvm_cnt | 0 | 1 | 0.00 | |||
| chip_sw_otp_ctrl_nvm_cnt | 10.129s | 0.000us | 0 | 1 | 0.00 | |
| chip_sw_otp_ctrl_sw_parts | 0 | 1 | 0.00 | |||
| chip_sw_otp_ctrl_sw_parts | 12.775s | 0.000us | 0 | 1 | 0.00 | |
| chip_sw_ast_clk_outputs | 0 | 1 | 0.00 | |||
| chip_sw_ast_clk_outputs | 8.761s | 0.000us | 0 | 1 | 0.00 | |
| chip_sw_ast_sys_clk_jitter | 1 | 7 | 14.29 | |||
| chip_sw_otbn_ecdsa_op_irq_jitter_en | 21.000s | 10.260us | 0 | 1 | 0.00 | |
| chip_sw_aes_enc_jitter_en | 30.000s | 10.380us | 0 | 1 | 0.00 | |
| chip_sw_hmac_enc_jitter_en | 25.000s | 10.380us | 0 | 1 | 0.00 | |
| chip_sw_keymgr_dpe_key_derivation_jitter_en | 30.000s | 10.380us | 0 | 1 | 0.00 | |
| chip_sw_kmac_mode_kmac_jitter_en | 22.000s | 10.100us | 0 | 1 | 0.00 | |
| chip_sw_sram_ctrl_scrambled_access_jitter_en | 10.772s | 0.000us | 0 | 1 | 0.00 | |
| chip_sw_clkmgr_jitter | 1051.000s | 160.929us | 1 | 1 | 100.00 | |
| chip_sw_soc_proxy_external_reset_requests | 0 | 1 | 0.00 | |||
| chip_sw_soc_proxy_smoketest | 949.000s | 157.272us | 0 | 1 | 0.00 | |
| chip_sw_soc_proxy_external_irqs | 0 | 1 | 0.00 | |||
| chip_sw_soc_proxy_smoketest | 949.000s | 157.272us | 0 | 1 | 0.00 | |
| chip_sw_soc_proxy_external_wakeup_requests | 0 | 1 | 0.00 | |||
| chip_sw_soc_proxy_external_wakeup | 943.000s | 157.631us | 0 | 1 | 0.00 | |
| chip_sw_soc_proxy_gpios | 1 | 1 | 100.00 | |||
| chip_sw_soc_proxy_gpios | 988.000s | 172.070us | 1 | 1 | 100.00 | |
| chip_sw_nmi_irq | 0 | 1 | 0.00 | |||
| chip_sw_rv_core_ibex_nmi_irq | 1779.000s | 271.154us | 0 | 1 | 0.00 | |
| chip_sw_rv_core_ibex_rnd | 1 | 1 | 100.00 | |||
| chip_sw_rv_core_ibex_rnd | 1386.000s | 214.149us | 1 | 1 | 100.00 | |
| chip_sw_rv_core_ibex_address_translation | 1 | 1 | 100.00 | |||
| chip_sw_rv_core_ibex_address_translation | 1184.000s | 183.657us | 1 | 1 | 100.00 | |
| chip_sw_rv_core_ibex_icache_scrambled_access | 1 | 1 | 100.00 | |||
| chip_sw_rv_core_ibex_icache_invalidate | 1101.000s | 180.166us | 1 | 1 | 100.00 | |
| chip_sw_rv_core_ibex_fault_dump | 0 | 1 | 0.00 | |||
| chip_sw_rstmgr_cpu_info | 2590.000s | 413.096us | 0 | 1 | 0.00 | |
| chip_sw_rv_core_ibex_double_fault | 0 | 1 | 0.00 | |||
| chip_sw_rstmgr_cpu_info | 2590.000s | 413.096us | 0 | 1 | 0.00 | |
| chip_sw_smoketest | 14 | 14 | 100.00 | |||
| chip_sw_aes_smoketest | 1069.000s | 175.400us | 1 | 1 | 100.00 | |
| chip_sw_aon_timer_smoketest | 1122.000s | 182.147us | 1 | 1 | 100.00 | |
| chip_sw_clkmgr_smoketest | 980.000s | 161.945us | 1 | 1 | 100.00 | |
| chip_sw_csrng_smoketest | 994.000s | 163.713us | 1 | 1 | 100.00 | |
| chip_sw_gpio_smoketest | 1107.000s | 192.284us | 1 | 1 | 100.00 | |
| chip_sw_hmac_smoketest | 1153.000s | 201.007us | 1 | 1 | 100.00 | |
| chip_sw_kmac_smoketest | 1105.000s | 189.732us | 1 | 1 | 100.00 | |
| chip_sw_otbn_smoketest | 1253.000s | 223.546us | 1 | 1 | 100.00 | |
| chip_sw_otp_ctrl_smoketest | 995.000s | 166.121us | 1 | 1 | 100.00 | |
| chip_sw_rv_plic_smoketest | 957.000s | 163.919us | 1 | 1 | 100.00 | |
| chip_sw_rv_timer_smoketest | 1302.000s | 267.603us | 1 | 1 | 100.00 | |
| chip_sw_rstmgr_smoketest | 975.000s | 161.072us | 1 | 1 | 100.00 | |
| chip_sw_sram_ctrl_smoketest | 971.000s | 164.268us | 1 | 1 | 100.00 | |
| chip_sw_uart_smoketest | 1023.000s | 174.593us | 1 | 1 | 100.00 | |
| chip_sw_rom_functests | 0 | 1 | 0.00 | |||
| rom_keymgr_functest | 12.368s | 0.000us | 0 | 1 | 0.00 | |
| chip_sw_signed | 0 | 1 | 0.00 | |||
| chip_sw_uart_smoketest_signed | 8.301s | 0.000us | 0 | 1 | 0.00 | |
| chip_sw_boot | 0 | 1 | 0.00 | |||
| chip_sw_uart_tx_rx_bootstrap | 100.225s | 0.000us | 0 | 1 | 0.00 | |
| chip_sw_secure_boot | 0 | 1 | 0.00 | |||
| base_rom_e2e_smoke | 11.310s | 0.000us | 0 | 1 | 0.00 | |
| chip_lc_scrap | 4 | 4 | 100.00 | |||
| chip_sw_lc_ctrl_rma_to_scrap | 1224.000s | 214.434us | 1 | 1 | 100.00 | |
| chip_sw_lc_ctrl_raw_to_scrap | 1191.000s | 214.794us | 1 | 1 | 100.00 | |
| chip_sw_lc_ctrl_test_locked0_to_scrap | 1180.000s | 229.079us | 1 | 1 | 100.00 | |
| chip_sw_lc_ctrl_rand_to_scrap | 1290.000s | 232.184us | 1 | 1 | 100.00 | |
| chip_lc_test_locked | 0 | 2 | 0.00 | |||
| chip_rv_dm_lc_disabled | 961.000s | 379.420us | 0 | 1 | 0.00 | |
| chip_sw_lc_walkthrough_testunlocks | 11.123s | 0.000us | 0 | 1 | 0.00 | |
| chip_sw_lc_walkthrough | 0 | 5 | 0.00 | |||
| chip_sw_lc_walkthrough_dev | 17.939s | 0.000us | 0 | 1 | 0.00 | |
| chip_sw_lc_walkthrough_prod | 14.877s | 0.000us | 0 | 1 | 0.00 | |
| chip_sw_lc_walkthrough_prodend | 16.734s | 0.000us | 0 | 1 | 0.00 | |
| chip_sw_lc_walkthrough_rma | 14.747s | 0.000us | 0 | 1 | 0.00 | |
| chip_sw_lc_walkthrough_testunlocks | 11.123s | 0.000us | 0 | 1 | 0.00 | |
| chip_sw_lc_ctrl_volatile_raw_unlock | 2 | 3 | 66.67 | |||
| chip_sw_lc_ctrl_volatile_raw_unlock | 3731.000s | 656.379us | 1 | 1 | 100.00 | |
| chip_sw_lc_ctrl_volatile_raw_unlock_ext_clk_48mhz | 3692.000s | 644.202us | 1 | 1 | 100.00 | |
| rom_volatile_raw_unlock | 7.732s | 0.000us | 0 | 1 | 0.00 | |
| chip_sw_rom_raw_unlock | 0 | 1 | 0.00 | |||
| rom_raw_unlock | 8.751s | 0.000us | 0 | 1 | 0.00 | |
| chip_sw_exit_test_unlocked_bootstrap | 0 | 1 | 0.00 | |||
| chip_sw_exit_test_unlocked_bootstrap | 92.393s | 0.000us | 0 | 1 | 0.00 | |
| chip_sw_inject_scramble_seed | 0 | 1 | 0.00 | |||
| chip_sw_inject_scramble_seed | 87.667s | 0.000us | 0 | 1 | 0.00 | |
| tl_d_oob_addr_access | 0 | 1 | 0.00 | |||
| chip_tl_errors | 274.000s | 118.169us | 0 | 1 | 0.00 | |
| tl_d_illegal_access | 0 | 1 | 0.00 | |||
| chip_tl_errors | 274.000s | 118.169us | 0 | 1 | 0.00 | |
| tl_d_outstanding_access | 0 | 2 | 0.00 | |||
| chip_csr_aliasing | 16.000s | 0.000us | 0 | 1 | 0.00 | |
| chip_same_csr_outstanding | 15.000s | 0.000us | 0 | 1 | 0.00 | |
| tl_d_partial_access | 0 | 2 | 0.00 | |||
| chip_csr_aliasing | 16.000s | 0.000us | 0 | 1 | 0.00 | |
| chip_same_csr_outstanding | 15.000s | 0.000us | 0 | 1 | 0.00 | |
| xbar_base_random_sequence | 0 | 1 | 0.00 | |||
| xbar_random | 37.000s | 17.204us | 0 | 1 | 0.00 | |
| xbar_random_delay | 0 | 6 | 0.00 | |||
| xbar_smoke_zero_delays | 31.000s | 12.514us | 0 | 1 | 0.00 | |
| xbar_smoke_large_delays | 302.000s | 2225.463us | 0 | 1 | 0.00 | |
| xbar_smoke_slow_rsp | 357.000s | 2187.225us | 0 | 1 | 0.00 | |
| xbar_random_zero_delays | 102.000s | 55.615us | 0 | 1 | 0.00 | |
| xbar_random_large_delays | 540.000s | 4645.165us | 0 | 1 | 0.00 | |
| xbar_random_slow_rsp | 1051.000s | 6827.012us | 0 | 1 | 0.00 | |
| xbar_unmapped_address | 0 | 2 | 0.00 | |||
| xbar_unmapped_addr | 76.000s | 23.232us | 0 | 1 | 0.00 | |
| xbar_error_and_unmapped_addr | 150.000s | 207.105us | 0 | 1 | 0.00 | |
| xbar_error_cases | 0 | 2 | 0.00 | |||
| xbar_error_random | 98.000s | 129.583us | 0 | 1 | 0.00 | |
| xbar_error_and_unmapped_addr | 150.000s | 207.105us | 0 | 1 | 0.00 | |
| xbar_all_access_same_device | 0 | 2 | 0.00 | |||
| xbar_access_same_device | 49.000s | 29.043us | 0 | 1 | 0.00 | |
| xbar_access_same_device_slow_rsp | 2829.000s | 20059.278us | 0 | 1 | 0.00 | |
| xbar_all_hosts_use_same_source_id | 0 | 1 | 0.00 | |||
| xbar_same_source | 55.000s | 27.665us | 0 | 1 | 0.00 | |
| xbar_stress_all | 0 | 2 | 0.00 | |||
| xbar_stress_all | 327.000s | 179.326us | 0 | 1 | 0.00 | |
| xbar_stress_all_with_error | 760.000s | 1612.766us | 0 | 1 | 0.00 | |
| xbar_stress_with_reset | 0 | 2 | 0.00 | |||
| xbar_stress_all_with_rand_reset | 1349.000s | 982.494us | 0 | 1 | 0.00 | |
| xbar_stress_all_with_reset_error | 863.000s | 1445.776us | 0 | 1 | 0.00 | |
| rom_e2e_smoke | 0 | 1 | 0.00 | |||
| rom_e2e_smoke | 12.024s | 0.000us | 0 | 1 | 0.00 | |
| rom_e2e_shutdown_output | 0 | 1 | 0.00 | |||
| rom_e2e_shutdown_output | 8.767s | 0.000us | 0 | 1 | 0.00 | |
| rom_e2e_shutdown_exception_c | 0 | 1 | 0.00 | |||
| rom_e2e_shutdown_exception_c | 11.722s | 0.000us | 0 | 1 | 0.00 | |
| rom_e2e_boot_policy_valid | 0 | 15 | 0.00 | |||
| rom_e2e_boot_policy_valid_a_good_b_good_test_unlocked0 | 8.641s | 0.000us | 0 | 1 | 0.00 | |
| rom_e2e_boot_policy_valid_a_good_b_good_dev | 8.597s | 0.000us | 0 | 1 | 0.00 | |
| rom_e2e_boot_policy_valid_a_good_b_good_prod | 10.530s | 0.000us | 0 | 1 | 0.00 | |
| rom_e2e_boot_policy_valid_a_good_b_good_prod_end | 10.061s | 0.000us | 0 | 1 | 0.00 | |
| rom_e2e_boot_policy_valid_a_good_b_good_rma | 9.803s | 0.000us | 0 | 1 | 0.00 | |
| rom_e2e_boot_policy_valid_a_good_b_bad_test_unlocked0 | 8.760s | 0.000us | 0 | 1 | 0.00 | |
| rom_e2e_boot_policy_valid_a_good_b_bad_dev | 8.659s | 0.000us | 0 | 1 | 0.00 | |
| rom_e2e_boot_policy_valid_a_good_b_bad_prod | 8.581s | 0.000us | 0 | 1 | 0.00 | |
| rom_e2e_boot_policy_valid_a_good_b_bad_prod_end | 8.403s | 0.000us | 0 | 1 | 0.00 | |
| rom_e2e_boot_policy_valid_a_good_b_bad_rma | 9.168s | 0.000us | 0 | 1 | 0.00 | |
| rom_e2e_boot_policy_valid_a_bad_b_good_test_unlocked0 | 8.869s | 0.000us | 0 | 1 | 0.00 | |
| rom_e2e_boot_policy_valid_a_bad_b_good_dev | 8.574s | 0.000us | 0 | 1 | 0.00 | |
| rom_e2e_boot_policy_valid_a_bad_b_good_prod | 8.810s | 0.000us | 0 | 1 | 0.00 | |
| rom_e2e_boot_policy_valid_a_bad_b_good_prod_end | 8.173s | 0.000us | 0 | 1 | 0.00 | |
| rom_e2e_boot_policy_valid_a_bad_b_good_rma | 9.347s | 0.000us | 0 | 1 | 0.00 | |
| rom_e2e_sigverify_always | 0 | 15 | 0.00 | |||
| rom_e2e_sigverify_always_a_bad_b_bad_test_unlocked0 | 8.899s | 0.000us | 0 | 1 | 0.00 | |
| rom_e2e_sigverify_always_a_bad_b_bad_dev | 9.214s | 0.000us | 0 | 1 | 0.00 | |
| rom_e2e_sigverify_always_a_bad_b_bad_prod | 8.525s | 0.000us | 0 | 1 | 0.00 | |
| rom_e2e_sigverify_always_a_bad_b_bad_prod_end | 8.673s | 0.000us | 0 | 1 | 0.00 | |
| rom_e2e_sigverify_always_a_bad_b_bad_rma | 8.926s | 0.000us | 0 | 1 | 0.00 | |
| rom_e2e_sigverify_always_a_bad_b_nothing_test_unlocked0 | 9.051s | 0.000us | 0 | 1 | 0.00 | |
| rom_e2e_sigverify_always_a_bad_b_nothing_dev | 8.389s | 0.000us | 0 | 1 | 0.00 | |
| rom_e2e_sigverify_always_a_bad_b_nothing_prod | 9.389s | 0.000us | 0 | 1 | 0.00 | |
| rom_e2e_sigverify_always_a_bad_b_nothing_prod_end | 8.180s | 0.000us | 0 | 1 | 0.00 | |
| rom_e2e_sigverify_always_a_bad_b_nothing_rma | 8.516s | 0.000us | 0 | 1 | 0.00 | |
| rom_e2e_sigverify_always_a_nothing_b_bad_test_unlocked0 | 8.543s | 0.000us | 0 | 1 | 0.00 | |
| rom_e2e_sigverify_always_a_nothing_b_bad_dev | 9.513s | 0.000us | 0 | 1 | 0.00 | |
| rom_e2e_sigverify_always_a_nothing_b_bad_prod | 8.331s | 0.000us | 0 | 1 | 0.00 | |
| rom_e2e_sigverify_always_a_nothing_b_bad_prod_end | 9.668s | 0.000us | 0 | 1 | 0.00 | |
| rom_e2e_sigverify_always_a_nothing_b_bad_rma | 9.221s | 0.000us | 0 | 1 | 0.00 | |
| rom_e2e_asm_init | 0 | 5 | 0.00 | |||
| rom_e2e_asm_init_test_unlocked0 | 8.592s | 0.000us | 0 | 1 | 0.00 | |
| rom_e2e_asm_init_dev | 9.024s | 0.000us | 0 | 1 | 0.00 | |
| rom_e2e_asm_init_prod | 8.591s | 0.000us | 0 | 1 | 0.00 | |
| rom_e2e_asm_init_prod_end | 8.921s | 0.000us | 0 | 1 | 0.00 | |
| rom_e2e_asm_init_rma | 9.071s | 0.000us | 0 | 1 | 0.00 | |
| rom_e2e_keymgr_init | 0 | 3 | 0.00 | |||
| rom_e2e_keymgr_init_rom_ext_meas | 7.850s | 0.000us | 0 | 1 | 0.00 | |
| rom_e2e_keymgr_init_rom_ext_no_meas | 8.077s | 0.000us | 0 | 1 | 0.00 | |
| rom_e2e_keymgr_init_rom_ext_invalid_meas | 8.659s | 0.000us | 0 | 1 | 0.00 | |
| rom_e2e_static_critical | 0 | 1 | 0.00 | |||
| rom_e2e_static_critical | 8.690s | 0.000us | 0 | 1 | 0.00 | |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| chip_sw_aes_masking_off | 1 | 1 | 100.00 | |||
| chip_sw_aes_masking_off | 1117.000s | 185.989us | 1 | 1 | 100.00 | |
| chip_sw_rv_core_ibex_lockstep_glitch | 1 | 1 | 100.00 | |||
| chip_sw_rv_core_ibex_lockstep_glitch | 706.000s | 119.378us | 1 | 1 | 100.00 | |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| chip_rv_dm_perform_debug | 0 | 3 | 0.00 | |||
| rom_e2e_jtag_debug_test_unlocked0 | 8.459s | 0.000us | 0 | 1 | 0.00 | |
| rom_e2e_jtag_debug_dev | 8.254s | 0.000us | 0 | 1 | 0.00 | |
| rom_e2e_jtag_debug_rma | 8.356s | 0.000us | 0 | 1 | 0.00 | |
| chip_sw_rv_dm_access_after_hw_reset | 0 | 1 | 0.00 | |||
| chip_sw_rv_dm_access_after_escalation_reset | 8.404s | 0.000us | 0 | 1 | 0.00 | |
| chip_sw_plic_alerts | 0 | 1 | 0.00 | |||
| chip_sw_all_escalation_resets | 1035.000s | 180.078us | 0 | 1 | 0.00 | |
| chip_sw_otp_ctrl_vendor_test_csr_access | 0 | 1 | 0.00 | |||
| chip_sw_otp_ctrl_vendor_test_csr_access | 12.939s | 0.000us | 0 | 1 | 0.00 | |
| chip_sw_otp_ctrl_escalation | 0 | 1 | 0.00 | |||
| chip_sw_otp_ctrl_escalation | 997.000s | 180.158us | 0 | 1 | 0.00 | |
| chip_sw_coremark | 0 | 1 | 0.00 | |||
| chip_sw_coremark | 10.677s | 0.000us | 0 | 1 | 0.00 | |
| chip_sw_power_max_load | 0 | 1 | 0.00 | |||
| chip_sw_power_virus | 9.664s | 0.000us | 0 | 1 | 0.00 | |
| rom_e2e_debug | 0 | 3 | 0.00 | |||
| rom_e2e_jtag_debug_test_unlocked0 | 8.459s | 0.000us | 0 | 1 | 0.00 | |
| rom_e2e_jtag_debug_dev | 8.254s | 0.000us | 0 | 1 | 0.00 | |
| rom_e2e_jtag_debug_rma | 8.356s | 0.000us | 0 | 1 | 0.00 | |
| rom_e2e_jtag_inject | 0 | 3 | 0.00 | |||
| rom_e2e_jtag_inject_test_unlocked0 | 8.198s | 0.000us | 0 | 1 | 0.00 | |
| rom_e2e_jtag_inject_dev | 8.435s | 0.000us | 0 | 1 | 0.00 | |
| rom_e2e_jtag_inject_rma | 8.765s | 0.000us | 0 | 1 | 0.00 | |
| rom_e2e_self_hash | 0 | 1 | 0.00 | |||
| rom_e2e_self_hash | 8.549s | 0.000us | 0 | 1 | 0.00 | |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| Unmapped | 8 | 20 | 40.00 | |||
| chip_sw_rstmgr_rst_cnsty_escalation | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| chip_sw_aes_gcm | 1325.000s | 207.046us | 1 | 1 | 100.00 | |
| chip_sw_entropy_src_kat_test | 1006.000s | 163.135us | 1 | 1 | 100.00 | |
| chip_sw_entropy_src_ast_rng_req | 1002.000s | 160.553us | 1 | 1 | 100.00 | |
| chip_plic_all_irqs_0 | 2244.000s | 365.197us | 1 | 1 | 100.00 | |
| chip_plic_all_irqs_10 | 1976.000s | 320.796us | 1 | 1 | 100.00 | |
| chip_sw_dma_inline_hashing | 1253.000s | 210.490us | 1 | 1 | 100.00 | |
| chip_sw_dma_abort | 1294.000s | 212.103us | 0 | 1 | 0.00 | |
| rom_e2e_sigverify_mod_exp_test_unlocked0_otbn | 8.963s | 0.000us | 0 | 1 | 0.00 | |
| rom_e2e_sigverify_mod_exp_test_unlocked0_sw | 8.658s | 0.000us | 0 | 1 | 0.00 | |
| rom_e2e_sigverify_mod_exp_dev_otbn | 8.095s | 0.000us | 0 | 1 | 0.00 | |
| rom_e2e_sigverify_mod_exp_dev_sw | 8.400s | 0.000us | 0 | 1 | 0.00 | |
| rom_e2e_sigverify_mod_exp_prod_otbn | 8.460s | 0.000us | 0 | 1 | 0.00 | |
| rom_e2e_sigverify_mod_exp_prod_sw | 8.514s | 0.000us | 0 | 1 | 0.00 | |
| rom_e2e_sigverify_mod_exp_prod_end_otbn | 8.045s | 0.000us | 0 | 1 | 0.00 | |
| rom_e2e_sigverify_mod_exp_prod_end_sw | 8.199s | 0.000us | 0 | 1 | 0.00 | |
| rom_e2e_sigverify_mod_exp_rma_otbn | 8.248s | 0.000us | 0 | 1 | 0.00 | |
| rom_e2e_sigverify_mod_exp_rma_sw | 8.658s | 0.000us | 0 | 1 | 0.00 | |
| chip_sw_entropy_src_smoketest | 1153.000s | 194.131us | 1 | 1 | 100.00 | |
| chip_sw_mbx_smoketest | 1444.000s | 317.795us | 1 | 1 | 100.00 | |
| Test | seed | line | log context | |
|---|---|---|---|---|
| xmsim: *E,ASRTST (/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-xcelium/cover_reg_top/fusesoc-work/src/lowrisc_tlul_socket_m1_*/rtl/tlul_socket_m*.sv,101): Assertion idInRange has failed | ||||
| chip_tl_errors | 72825408389616201329339770217845080137390310654220063737547684229740830510769 | 201 |
xmsim: *E,ASRTST (/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-xcelium/cover_reg_top/fusesoc-work/src/lowrisc_tlul_socket_m1_0.1/rtl/tlul_socket_m1.sv,101): (time 118169500 PS) Assertion tb.dut.top_darjeeling.u_soc_proxy.u_ctn_egress_mux.gen_host_fifo[0].idInRange has failed
UVM_ERROR @ 118.169500 us: (tlul_socket_m1.sv:101) [ASSERT FAILED] idInRange
UVM_INFO @ 118.169500 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| UVM_ERROR @ * us: (cip_base_vseq.sv:649) [chip_rv_dm_lc_disabled_vseq] Check failed masked_data == exp_data (* [*] vs * [*]) addr * read out mismatch | ||||
| chip_rv_dm_lc_disabled | 28860089207618810022021487826249311499127456137083531609376112563988171903713 | 216 |
UVM_ERROR @ 379.419500 us: (cip_base_vseq.sv:649) [uvm_test_top.env.virtual_sequencer.chip_rv_dm_lc_disabled_vseq] Check failed masked_data == exp_data (0 [0x0] vs 4294967295 [0xffffffff]) addr 0x407d4 read out mismatch
UVM_INFO @ 379.419500 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| UVM_FATAL @ * us: (dv_base_test.sv:132) [uvm_test_top] Check failed (test_seq.randomize()) Randomization failed! | ||||
| chip_padctrl_attributes | 14656481217605741985382060458094666637252306934590004595637223983977966433332 | 214 |
UVM_FATAL @ 0.000000 us: (dv_base_test.sv:132) [uvm_test_top] Check failed (test_seq.randomize()) Randomization failed!
UVM_INFO @ 0.000000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| UVM_FATAL @ * us: (mem_bkdr_util.sv:597) [mem_bkdr_util[Otp]] file otp_ctrl_img_rma.vmem could not be opened for r mode | ||||
| chip_csr_bit_bash | 77514568664762390084693778605807960204672718530107913990054255584710052307836 | 102 |
UVM_FATAL @ 0.000000 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[Otp]] file otp_ctrl_img_rma.vmem could not be opened for r mode
UVM_INFO @ 0.000000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| chip_csr_aliasing | 65134951510139940805644578721331417045307113067029448836914388714188761509796 | 102 |
UVM_FATAL @ 0.000000 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[Otp]] file otp_ctrl_img_rma.vmem could not be opened for r mode
UVM_INFO @ 0.000000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| chip_same_csr_outstanding | 22412651731707481541317001051760427746666341263930479878997670751307101510956 | 102 |
UVM_FATAL @ 0.000000 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[Otp]] file otp_ctrl_img_rma.vmem could not be opened for r mode
UVM_INFO @ 0.000000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| UVM_FATAL @ * us: (mem_bkdr_util.sv:597) [mem_bkdr_util[Rom0]] file example_test_from_rom_rom_prog_sim_dv.*.scr.vmem could not be opened for r mode | ||||
| chip_sw_example_rom | 35710196690165405562739778508945857620627708723125269274889982944019970889199 | 250 |
UVM_FATAL @ 10.380001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[Rom0]] file example_test_from_rom_rom_prog_sim_dv.39.scr.vmem could not be opened for r mode
UVM_INFO @ 10.380001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| Job returned non-zero exit code | ||||
| chip_sw_example_manufacturer | 30084493160622029852207992233174052635820106859075941108905230136785855654987 | None |
Use --verbose_failures to see the command lines of failed build steps.
ERROR: Analysis of target '@@+hooks+manufacturer_test_hooks//:example_test_sim_dv' failed; build aborted: Target @@+hooks+manufacturer_test_hooks//:example_test_sim_dv is incompatible and cannot be built, but was explicitly requested.
Dependency chain:
@@+hooks+manufacturer_test_hooks//:example_test_sim_dv (b853eb) <-- target platform (//toolchain:opentitan_platform) didn't satisfy constraint @@platforms//:incompatible
INFO: Elapsed time: 66.718s, Critical Path: 0.01s
INFO: 1 process: 1 internal.
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
|
|
| chip_sw_data_integrity_escalation | 9724691783689575489503120476892194822569174874667710699424645804052738526809 | None |
Use --verbose_failures to see the command lines of failed build steps.
ERROR: Analysis of target '//sw/device/tests/sim_dv:data_integrity_escalation_reset_test_sim_dv' failed; build aborted: Target //sw/device/tests/sim_dv:data_integrity_escalation_reset_test_sim_dv is incompatible and cannot be built, but was explicitly requested.
Dependency chain:
//sw/device/tests/sim_dv:data_integrity_escalation_reset_test_sim_dv (b853eb) <-- target platform (//toolchain:opentitan_platform) didn't satisfy constraint @@platforms//:incompatible
INFO: Elapsed time: 39.086s, Critical Path: 0.03s
INFO: 1 process: 1 internal.
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
|
|
| chip_sw_sleep_pin_wake | 29893920320748995993551539478335270819112140041114255727714407437689482446343 | None |
Use --verbose_failures to see the command lines of failed build steps.
ERROR: Analysis of target '//sw/device/tests:sleep_pin_wake_test_sim_dv' failed; build aborted: Target //sw/device/tests:sleep_pin_wake_test_sim_dv is incompatible and cannot be built, but was explicitly requested.
Dependency chain:
//sw/device/tests:sleep_pin_wake_test_sim_dv (b853eb) <-- target platform (//toolchain:opentitan_platform) didn't satisfy constraint @@platforms//:incompatible
INFO: Elapsed time: 67.248s, Critical Path: 0.03s
INFO: 1 process: 1 internal.
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
|
|
| chip_sw_sleep_pin_retention | 32711121680457210927791405033792913084080233326665195289648349191698103149747 | None |
Use --verbose_failures to see the command lines of failed build steps.
ERROR: Analysis of target '//sw/device/tests:sleep_pin_retention_test_sim_dv' failed; build aborted: Target //sw/device/tests:sleep_pin_retention_test_sim_dv is incompatible and cannot be built, but was explicitly requested.
Dependency chain:
//sw/device/tests:sleep_pin_retention_test_sim_dv (b853eb) <-- target platform (//toolchain:opentitan_platform) didn't satisfy constraint @@platforms//:incompatible
INFO: Elapsed time: 10.232s, Critical Path: 0.03s
INFO: 1 process: 1 internal.
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
|
|
| chip_sw_uart_tx_rx | 86728741812084654798595184250483526598901433573159085248665141905812191215325 | None |
Use --verbose_failures to see the command lines of failed build steps.
ERROR: Analysis of target '//sw/device/tests:uart_tx_rx_test_sim_dv' failed; build aborted: Target //sw/device/tests:uart_tx_rx_test_sim_dv is incompatible and cannot be built, but was explicitly requested.
Dependency chain:
//sw/device/tests:uart_tx_rx_test_sim_dv (b853eb) <-- target platform (//toolchain:opentitan_platform) didn't satisfy constraint @@platforms//:incompatible
INFO: Elapsed time: 1.256s, Critical Path: 0.03s
INFO: 1 process: 1 internal.
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
|
|
| chip_sw_uart_tx_rx_bootstrap | 27630304984351888381843206975915314717032615274885948878091280865883834484458 | None |
Use --verbose_failures to see the command lines of failed build steps.
ERROR: Analysis of target '//sw/device/tests:uart_tx_rx_test_sim_dv' failed; build aborted: Target //sw/device/tests:uart_tx_rx_test_sim_dv is incompatible and cannot be built, but was explicitly requested.
Dependency chain:
//sw/device/tests:uart_tx_rx_test_sim_dv (b853eb) <-- target platform (//toolchain:opentitan_platform) didn't satisfy constraint @@platforms//:incompatible
INFO: Elapsed time: 0.712s, Critical Path: 0.03s
INFO: 1 process: 1 internal.
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
|
|
| chip_sw_inject_scramble_seed | 3076676723544989417911362307410869630064409396581939993640278445644217615050 | None |
Use --verbose_failures to see the command lines of failed build steps.
ERROR: Analysis of target '//sw/device/tests/sim_dv:inject_scramble_seed_sim_dv' failed; build aborted: Target //sw/device/tests/sim_dv:inject_scramble_seed_sim_dv is incompatible and cannot be built, but was explicitly requested.
Dependency chain:
//sw/device/tests/sim_dv:inject_scramble_seed_sim_dv (b853eb) <-- target platform (//toolchain:opentitan_platform) didn't satisfy constraint @@platforms//:incompatible
INFO: Elapsed time: 65.503s, Critical Path: 0.04s
INFO: 1 process: 1 internal.
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
|
|
| chip_sw_exit_test_unlocked_bootstrap | 42793155611850144742050811967030079847770194494493646549791885479652971720600 | None |
Use --verbose_failures to see the command lines of failed build steps.
ERROR: Analysis of target '//sw/device/tests/sim_dv:exit_test_unlocked_bootstrap_sim_dv' failed; build aborted: Target //sw/device/tests/sim_dv:exit_test_unlocked_bootstrap_sim_dv is incompatible and cannot be built, but was explicitly requested.
Dependency chain:
//sw/device/tests/sim_dv:exit_test_unlocked_bootstrap_sim_dv (b853eb) <-- target platform (//toolchain:opentitan_platform) didn't satisfy constraint @@platforms//:incompatible
INFO: Elapsed time: 70.735s, Critical Path: 0.03s
INFO: 1 process: 1 internal.
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
|
|
| chip_sw_uart_rand_baudrate | 106670165157817497750448796565406979949486800630530254013593017917915616091133 | None |
ERROR: Analysis of target '//sw/device/tests:uart_tx_rx_test_sim_dv' failed; build aborted: Target //sw/device/tests:uart_tx_rx_test_sim_dv is incompatible and cannot be built, but was explicitly requested.
Dependency chain:
//sw/device/tests:uart_tx_rx_test_sim_dv (b853eb) <-- target platform (//toolchain:opentitan_platform) didn't satisfy constraint @@platforms//:incompatible
INFO: Elapsed time: 69.258s, Critical Path: 0.06s
INFO: 1 process: 1 internal.
ERROR: Build did NOT complete successfully
FAILED:
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
|
|
| chip_sw_uart_tx_rx_alt_clk_freq | 89228606761479706675147343610552631602132839613685329705566150029730129022271 | None |
Use --verbose_failures to see the command lines of failed build steps.
ERROR: Analysis of target '//sw/device/tests:uart_tx_rx_test_sim_dv' failed; build aborted: Target //sw/device/tests:uart_tx_rx_test_sim_dv is incompatible and cannot be built, but was explicitly requested.
Dependency chain:
//sw/device/tests:uart_tx_rx_test_sim_dv (b853eb) <-- target platform (//toolchain:opentitan_platform) didn't satisfy constraint @@platforms//:incompatible
INFO: Elapsed time: 11.339s, Critical Path: 0.02s
INFO: 1 process: 1 internal.
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
|
|
| chip_sw_i2c_host_tx_rx | 15874129878885586079900508933158321962204075807280664448688268044060232069042 | None |
Use --verbose_failures to see the command lines of failed build steps.
ERROR: Analysis of target '//sw/device/tests/sim_dv:i2c_host_tx_rx_test_sim_dv' failed; build aborted: Target //sw/device/tests/sim_dv:i2c_host_tx_rx_test_sim_dv is incompatible and cannot be built, but was explicitly requested.
Dependency chain:
//sw/device/tests/sim_dv:i2c_host_tx_rx_test_sim_dv (b853eb) <-- target platform (//toolchain:opentitan_platform) didn't satisfy constraint @@platforms//:incompatible
INFO: Elapsed time: 2.679s, Critical Path: 0.03s
INFO: 1 process: 1 internal.
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
|
|
| chip_sw_i2c_device_tx_rx | 26781080176914962316473406095609420089339137123433076549267606071351014485595 | None |
Use --verbose_failures to see the command lines of failed build steps.
ERROR: Analysis of target '//sw/device/tests/sim_dv:i2c_device_tx_rx_test_sim_dv' failed; build aborted: Target //sw/device/tests/sim_dv:i2c_device_tx_rx_test_sim_dv is incompatible and cannot be built, but was explicitly requested.
Dependency chain:
//sw/device/tests/sim_dv:i2c_device_tx_rx_test_sim_dv (b853eb) <-- target platform (//toolchain:opentitan_platform) didn't satisfy constraint @@platforms//:incompatible
INFO: Elapsed time: 4.186s, Critical Path: 0.02s
INFO: 1 process: 1 internal.
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
|
|
| chip_sw_spi_device_tpm | 115275016710131810060010590937654407182108603002466516660466601268051909523748 | None |
Use --verbose_failures to see the command lines of failed build steps.
ERROR: Analysis of target '//sw/device/tests:spi_device_tpm_tx_rx_test_sim_dv' failed; build aborted: Target //sw/device/tests:spi_device_tpm_tx_rx_test_sim_dv is incompatible and cannot be built, but was explicitly requested.
Dependency chain:
//sw/device/tests:spi_device_tpm_tx_rx_test_sim_dv (b853eb) <-- target platform (//toolchain:opentitan_platform) didn't satisfy constraint @@platforms//:incompatible
INFO: Elapsed time: 1.431s, Critical Path: 0.08s
INFO: 1 process: 1 internal.
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
|
|
| chip_sw_spi_host_tx_rx | 91166694194205908947676400035512886772782070185735245174792889801643359989142 | None |
Use --verbose_failures to see the command lines of failed build steps.
ERROR: Analysis of target '//sw/device/tests/sim_dv:spi_host_tx_rx_test_sim_dv' failed; build aborted: Target //sw/device/tests/sim_dv:spi_host_tx_rx_test_sim_dv is incompatible and cannot be built, but was explicitly requested.
Dependency chain:
//sw/device/tests/sim_dv:spi_host_tx_rx_test_sim_dv (b853eb) <-- target platform (//toolchain:opentitan_platform) didn't satisfy constraint @@platforms//:incompatible
INFO: Elapsed time: 1.205s, Critical Path: 0.02s
INFO: 1 process: 1 internal.
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
|
|
| chip_sw_lc_ctrl_otp_hw_cfg | 95735975204928938253461761550117848495962806348017271085043037094279067101433 | None |
---- STDERR ----
Another command (pid=143800) is running. Waiting for it to complete on the server (server_pid=65989)...
Another command (pid=146352) is running. Waiting for it to complete on the server (server_pid=65989)...
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/tests:lc_ctrl_otp_hw_cfg_test_sim_dv': no such target '//sw/device/tests:lc_ctrl_otp_hw_cfg_test_sim_dv': target 'lc_ctrl_otp_hw_cfg_test_sim_dv' not declared in package 'sw/device/tests' defined by /nightly/current_run/opentitan/sw/device/tests/BUILD (did you mean lc_ctrl_otp_hw_cfg0_test_sim_dv?)
ERROR: no such target '//sw/device/tests:lc_ctrl_otp_hw_cfg_test_sim_dv': target 'lc_ctrl_otp_hw_cfg_test_sim_dv' not declared in package 'sw/device/tests' defined by /nightly/current_run/opentitan/sw/device/tests/BUILD (did you mean lc_ctrl_otp_hw_cfg0_test_sim_dv?)
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
|
|
| chip_sw_otp_ctrl_lc_signals_test_unlocked0 | 107023150625720107064321968390735680897859609207239069440751219081421861406392 | None |
Use --verbose_failures to see the command lines of failed build steps.
ERROR: Analysis of target '//sw/device/tests/sim_dv:otp_ctrl_lc_signals_test_sim_dv' failed; build aborted: Target //sw/device/tests/sim_dv:otp_ctrl_lc_signals_test_sim_dv is incompatible and cannot be built, but was explicitly requested.
Dependency chain:
//sw/device/tests/sim_dv:otp_ctrl_lc_signals_test_sim_dv (b853eb) <-- target platform (//toolchain:opentitan_platform) didn't satisfy constraint @@platforms//:incompatible
INFO: Elapsed time: 6.645s, Critical Path: 0.02s
INFO: 1 process: 1 internal.
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
|
|
| chip_sw_otp_ctrl_lc_signals_dev | 58707592123325442303334238674726806872212721643768450371889922817950690816311 | None |
Use --verbose_failures to see the command lines of failed build steps.
ERROR: Analysis of target '//sw/device/tests/sim_dv:otp_ctrl_lc_signals_test_sim_dv' failed; build aborted: Target //sw/device/tests/sim_dv:otp_ctrl_lc_signals_test_sim_dv is incompatible and cannot be built, but was explicitly requested.
Dependency chain:
//sw/device/tests/sim_dv:otp_ctrl_lc_signals_test_sim_dv (b853eb) <-- target platform (//toolchain:opentitan_platform) didn't satisfy constraint @@platforms//:incompatible
INFO: Elapsed time: 0.651s, Critical Path: 0.01s
INFO: 1 process: 1 internal.
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
|
|
| chip_sw_otp_ctrl_lc_signals_prod | 33147914634772096617467953521679559868199775370521151253263093866329959502606 | None |
Use --verbose_failures to see the command lines of failed build steps.
ERROR: Analysis of target '//sw/device/tests/sim_dv:otp_ctrl_lc_signals_test_sim_dv' failed; build aborted: Target //sw/device/tests/sim_dv:otp_ctrl_lc_signals_test_sim_dv is incompatible and cannot be built, but was explicitly requested.
Dependency chain:
//sw/device/tests/sim_dv:otp_ctrl_lc_signals_test_sim_dv (b853eb) <-- target platform (//toolchain:opentitan_platform) didn't satisfy constraint @@platforms//:incompatible
INFO: Elapsed time: 7.062s, Critical Path: 0.02s
INFO: 1 process: 1 internal.
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
|
|
| chip_sw_otp_ctrl_lc_signals_rma | 60610290694273552483811485762783951973173258086625721630298545175155500998128 | None |
Use --verbose_failures to see the command lines of failed build steps.
ERROR: Analysis of target '//sw/device/tests/sim_dv:otp_ctrl_lc_signals_test_sim_dv' failed; build aborted: Target //sw/device/tests/sim_dv:otp_ctrl_lc_signals_test_sim_dv is incompatible and cannot be built, but was explicitly requested.
Dependency chain:
//sw/device/tests/sim_dv:otp_ctrl_lc_signals_test_sim_dv (b853eb) <-- target platform (//toolchain:opentitan_platform) didn't satisfy constraint @@platforms//:incompatible
INFO: Elapsed time: 0.704s, Critical Path: 0.03s
INFO: 1 process: 1 internal.
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
|
|
| chip_sw_otp_ctrl_vendor_test_csr_access | 6107312402304923981016901615116435499541628453484578746766089514455339495632 | None |
Use --verbose_failures to see the command lines of failed build steps.
ERROR: Analysis of target '//sw/device/tests/sim_dv:otp_ctrl_vendor_test_csr_access_test_sim_dv' failed; build aborted: Target //sw/device/tests/sim_dv:otp_ctrl_vendor_test_csr_access_test_sim_dv is incompatible and cannot be built, but was explicitly requested.
Dependency chain:
//sw/device/tests/sim_dv:otp_ctrl_vendor_test_csr_access_test_sim_dv (b853eb) <-- target platform (//toolchain:opentitan_platform) didn't satisfy constraint @@platforms//:incompatible
INFO: Elapsed time: 1.707s, Critical Path: 0.02s
INFO: 1 process: 1 internal.
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
|
|
| chip_sw_otp_ctrl_nvm_cnt | 65070777444597382691463222589938954381021413537884604965134025017121060828436 | None |
Another command (pid=174640) is running. Waiting for it to complete on the server (server_pid=65989)...
Another command (pid=177000) is running. Waiting for it to complete on the server (server_pid=65989)...
Another command (pid=175805) is running. Waiting for it to complete on the server (server_pid=65989)...
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/tests:otp_ctrl_nvm_cnt_test_sim_dv': no such target '//sw/device/tests:otp_ctrl_nvm_cnt_test_sim_dv': target 'otp_ctrl_nvm_cnt_test_sim_dv' not declared in package 'sw/device/tests' defined by /nightly/current_run/opentitan/sw/device/tests/BUILD
ERROR: no such target '//sw/device/tests:otp_ctrl_nvm_cnt_test_sim_dv': target 'otp_ctrl_nvm_cnt_test_sim_dv' not declared in package 'sw/device/tests' defined by /nightly/current_run/opentitan/sw/device/tests/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
|
|
| chip_sw_otp_ctrl_sw_parts | 581914312951359031370283259678668846382657978901121560822170329095514443583 | None |
Another command (pid=180049) is running. Waiting for it to complete on the server (server_pid=65989)...
Another command (pid=182361) is running. Waiting for it to complete on the server (server_pid=65989)...
Another command (pid=179056) is running. Waiting for it to complete on the server (server_pid=65989)...
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/tests:otp_ctrl_sw_parts_test_sim_dv': no such target '//sw/device/tests:otp_ctrl_sw_parts_test_sim_dv': target 'otp_ctrl_sw_parts_test_sim_dv' not declared in package 'sw/device/tests' defined by /nightly/current_run/opentitan/sw/device/tests/BUILD
ERROR: no such target '//sw/device/tests:otp_ctrl_sw_parts_test_sim_dv': target 'otp_ctrl_sw_parts_test_sim_dv' not declared in package 'sw/device/tests' defined by /nightly/current_run/opentitan/sw/device/tests/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
|
|
| chip_sw_lc_ctrl_transition | 54088000386783904306068329425923171542559365304636925779784135901841012969902 | None |
Use --verbose_failures to see the command lines of failed build steps.
ERROR: Analysis of target '//sw/device/tests/sim_dv:lc_ctrl_transition_test_sim_dv' failed; build aborted: Target //sw/device/tests/sim_dv:lc_ctrl_transition_test_sim_dv is incompatible and cannot be built, but was explicitly requested.
Dependency chain:
//sw/device/tests/sim_dv:lc_ctrl_transition_test_sim_dv (b853eb) <-- target platform (//toolchain:opentitan_platform) didn't satisfy constraint @@platforms//:incompatible
INFO: Elapsed time: 4.607s, Critical Path: 0.02s
INFO: 1 process: 1 internal.
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
|
|
| chip_sw_lc_walkthrough_dev | 31926777637579471413568892515419583611226067957692845375073676141103320591719 | None |
ERROR: Analysis of target '//sw/device/tests/sim_dv:lc_walkthrough_test_sim_dv' failed; build aborted: Target //sw/device/tests/sim_dv:lc_walkthrough_test_sim_dv is incompatible and cannot be built, but was explicitly requested.
Dependency chain:
//sw/device/tests/sim_dv:lc_walkthrough_test_sim_dv (b853eb) <-- target platform (//toolchain:opentitan_platform) didn't satisfy constraint @@platforms//:incompatible
INFO: Elapsed time: 5.721s, Critical Path: 0.04s
INFO: 1 process: 1 internal.
ERROR: Build did NOT complete successfully
FAILED:
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
|
|
| chip_sw_lc_walkthrough_prod | 84975245714319104065485046479593430828215930562553297164316503088829726930842 | None |
Use --verbose_failures to see the command lines of failed build steps.
ERROR: Analysis of target '//sw/device/tests/sim_dv:lc_walkthrough_test_sim_dv' failed; build aborted: Target //sw/device/tests/sim_dv:lc_walkthrough_test_sim_dv is incompatible and cannot be built, but was explicitly requested.
Dependency chain:
//sw/device/tests/sim_dv:lc_walkthrough_test_sim_dv (b853eb) <-- target platform (//toolchain:opentitan_platform) didn't satisfy constraint @@platforms//:incompatible
INFO: Elapsed time: 2.100s, Critical Path: 0.03s
INFO: 1 process: 1 internal.
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
|
|
| chip_sw_lc_walkthrough_prodend | 90608391048397972075889449480864856782941618468421787312729680467463453924080 | None |
Use --verbose_failures to see the command lines of failed build steps.
ERROR: Analysis of target '//sw/device/tests/sim_dv:lc_walkthrough_test_sim_dv' failed; build aborted: Target //sw/device/tests/sim_dv:lc_walkthrough_test_sim_dv is incompatible and cannot be built, but was explicitly requested.
Dependency chain:
//sw/device/tests/sim_dv:lc_walkthrough_test_sim_dv (b853eb) <-- target platform (//toolchain:opentitan_platform) didn't satisfy constraint @@platforms//:incompatible
INFO: Elapsed time: 4.961s, Critical Path: 0.00s
INFO: 1 process: 1 internal.
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
|
|
| chip_sw_lc_walkthrough_rma | 99359166978825108496074497203853069134023917266816262462476149869329287338668 | None |
Use --verbose_failures to see the command lines of failed build steps.
ERROR: Analysis of target '//sw/device/tests/sim_dv:lc_walkthrough_test_sim_dv' failed; build aborted: Target //sw/device/tests/sim_dv:lc_walkthrough_test_sim_dv is incompatible and cannot be built, but was explicitly requested.
Dependency chain:
//sw/device/tests/sim_dv:lc_walkthrough_test_sim_dv (b853eb) <-- target platform (//toolchain:opentitan_platform) didn't satisfy constraint @@platforms//:incompatible
INFO: Elapsed time: 0.506s, Critical Path: 0.01s
INFO: 1 process: 1 internal.
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
|
|
| chip_sw_lc_walkthrough_testunlocks | 79487123108078085555904109778360059583626428973613135435434253266863046445228 | None |
ERROR: Analysis of target '//sw/device/tests/sim_dv:lc_walkthrough_testunlocks_test_sim_dv' failed; build aborted: Target //sw/device/tests/sim_dv:lc_walkthrough_testunlocks_test_sim_dv is incompatible and cannot be built, but was explicitly requested.
Dependency chain:
//sw/device/tests/sim_dv:lc_walkthrough_testunlocks_test_sim_dv (b853eb) <-- target platform (//toolchain:opentitan_platform) didn't satisfy constraint @@platforms//:incompatible
INFO: Elapsed time: 1.859s, Critical Path: 0.08s
INFO: 1 process: 1 internal.
ERROR: Build did NOT complete successfully
FAILED:
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
|
|
| chip_sw_pwrmgr_main_power_glitch_reset | 59895590356370266022935517288332096115510292170726893541457396690143176202136 | None |
Use --verbose_failures to see the command lines of failed build steps.
ERROR: Analysis of target '//sw/device/tests/sim_dv:pwrmgr_main_power_glitch_test_sim_dv' failed; build aborted: Target //sw/device/tests/sim_dv:pwrmgr_main_power_glitch_test_sim_dv is incompatible and cannot be built, but was explicitly requested.
Dependency chain:
//sw/device/tests/sim_dv:pwrmgr_main_power_glitch_test_sim_dv (b853eb) <-- target platform (//toolchain:opentitan_platform) didn't satisfy constraint @@platforms//:incompatible
INFO: Elapsed time: 0.339s, Critical Path: 0.03s
INFO: 1 process: 1 internal.
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
|
|
| chip_sw_pwrmgr_sleep_power_glitch_reset | 36830486416753088082304382073722624572795261917367412609510324645002255681062 | None |
Use --verbose_failures to see the command lines of failed build steps.
ERROR: Analysis of target '//sw/device/tests/sim_dv:pwrmgr_sleep_power_glitch_test_sim_dv' failed; build aborted: Target //sw/device/tests/sim_dv:pwrmgr_sleep_power_glitch_test_sim_dv is incompatible and cannot be built, but was explicitly requested.
Dependency chain:
//sw/device/tests/sim_dv:pwrmgr_sleep_power_glitch_test_sim_dv (b853eb) <-- target platform (//toolchain:opentitan_platform) didn't satisfy constraint @@platforms//:incompatible
INFO: Elapsed time: 0.283s, Critical Path: 0.04s
INFO: 1 process: 1 internal.
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
|
|
| chip_sw_pwrmgr_deep_sleep_power_glitch_reset | 109519791491934728012415632632206735620313632785581890421331013510620468120076 | None |
Use --verbose_failures to see the command lines of failed build steps.
ERROR: Analysis of target '//sw/device/tests/sim_dv:pwrmgr_deep_sleep_power_glitch_test_sim_dv' failed; build aborted: Target //sw/device/tests/sim_dv:pwrmgr_deep_sleep_power_glitch_test_sim_dv is incompatible and cannot be built, but was explicitly requested.
Dependency chain:
//sw/device/tests/sim_dv:pwrmgr_deep_sleep_power_glitch_test_sim_dv (b853eb) <-- target platform (//toolchain:opentitan_platform) didn't satisfy constraint @@platforms//:incompatible
INFO: Elapsed time: 0.303s, Critical Path: 0.01s
INFO: 1 process: 1 internal.
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
|
|
| chip_sw_pwrmgr_random_sleep_power_glitch_reset | 82183937252506054195447675837732736294096378165610822944241965521572891690947 | None |
Use --verbose_failures to see the command lines of failed build steps.
ERROR: Analysis of target '//sw/device/tests/sim_dv:pwrmgr_random_sleep_power_glitch_reset_test_sim_dv' failed; build aborted: Target //sw/device/tests/sim_dv:pwrmgr_random_sleep_power_glitch_reset_test_sim_dv is incompatible and cannot be built, but was explicitly requested.
Dependency chain:
//sw/device/tests/sim_dv:pwrmgr_random_sleep_power_glitch_reset_test_sim_dv (b853eb) <-- target platform (//toolchain:opentitan_platform) didn't satisfy constraint @@platforms//:incompatible
INFO: Elapsed time: 0.291s, Critical Path: 0.02s
INFO: 1 process: 1 internal.
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
|
|
| chip_sw_pwrmgr_sleep_disabled | 100676913274886469930172395996293773027224412109009557675676765874012774638109 | None |
Use --verbose_failures to see the command lines of failed build steps.
ERROR: Analysis of target '//sw/device/tests:pwrmgr_sleep_disabled_test_sim_dv' failed; build aborted: Target //sw/device/tests:pwrmgr_sleep_disabled_test_sim_dv is incompatible and cannot be built, but was explicitly requested.
Dependency chain:
//sw/device/tests:pwrmgr_sleep_disabled_test_sim_dv (b853eb) <-- target platform (//toolchain:opentitan_platform) didn't satisfy constraint @@platforms//:incompatible
INFO: Elapsed time: 0.291s, Critical Path: 0.03s
INFO: 1 process: 1 internal.
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
|
|
| chip_sw_pwrmgr_wdog_reset | 108578633535995936217542613784085904077398303203240458880467753901294408073371 | None |
Use --verbose_failures to see the command lines of failed build steps.
ERROR: Analysis of target '//sw/device/tests:pwrmgr_wdog_reset_reqs_test_sim_dv' failed; build aborted: Target //sw/device/tests:pwrmgr_wdog_reset_reqs_test_sim_dv is incompatible and cannot be built, but was explicitly requested.
Dependency chain:
//sw/device/tests:pwrmgr_wdog_reset_reqs_test_sim_dv (b853eb) <-- target platform (//toolchain:opentitan_platform) didn't satisfy constraint @@platforms//:incompatible
INFO: Elapsed time: 0.373s, Critical Path: 0.05s
INFO: 1 process: 1 internal.
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
|
|
| chip_sw_alert_test | 57561422471370470130670323744290101214951042898254999335110401734160461492566 | None |
---- STDERR ----
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/tests/autogen/top_darjeeling:alert_test_sim_dv': no such package 'sw/device/tests/autogen/top_darjeeling': BUILD file not found in any of the following directories. Add a BUILD file to a directory to mark it as a package.
- sw/device/tests/autogen/top_darjeeling
ERROR: no such package 'sw/device/tests/autogen/top_darjeeling': BUILD file not found in any of the following directories. Add a BUILD file to a directory to mark it as a package.
- sw/device/tests/autogen/top_darjeeling
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
|
|
| chip_sw_alert_handler_escalation | 112015475910558729443689039223388470971002267529647182840557771936770354099568 | None |
Use --verbose_failures to see the command lines of failed build steps.
ERROR: Analysis of target '//sw/device/tests:alert_handler_escalation_test_sim_dv' failed; build aborted: Target //sw/device/tests:alert_handler_escalation_test_sim_dv is incompatible and cannot be built, but was explicitly requested.
Dependency chain:
//sw/device/tests:alert_handler_escalation_test_sim_dv (b853eb) <-- target platform (//toolchain:opentitan_platform) didn't satisfy constraint @@platforms//:incompatible
INFO: Elapsed time: 0.291s, Critical Path: 0.03s
INFO: 1 process: 1 internal.
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
|
|
| chip_sw_alert_handler_reverse_ping_in_deep_sleep | 34485475094150015828643934331677228082959402033062150001356782372549299944644 | None |
Use --verbose_failures to see the command lines of failed build steps.
ERROR: Analysis of target '//sw/device/tests:alert_handler_reverse_ping_in_deep_sleep_test_sim_dv' failed; build aborted: Target //sw/device/tests:alert_handler_reverse_ping_in_deep_sleep_test_sim_dv is incompatible and cannot be built, but was explicitly requested.
Dependency chain:
//sw/device/tests:alert_handler_reverse_ping_in_deep_sleep_test_sim_dv (b853eb) <-- target platform (//toolchain:opentitan_platform) didn't satisfy constraint @@platforms//:incompatible
INFO: Elapsed time: 1.001s, Critical Path: 0.05s
INFO: 1 process: 1 internal.
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
|
|
| chip_sw_alert_handler_lpg_sleep_mode_alerts | 15868618114944243078125545207756914689277288981133390477014312921171081926528 | None |
---- STDOUT ----
---- STDERR ----
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/tests:alert_handler_lpg_sleep_mode_alerts_test_sim_dv': no such target '//sw/device/tests:alert_handler_lpg_sleep_mode_alerts_test_sim_dv': target 'alert_handler_lpg_sleep_mode_alerts_test_sim_dv' not declared in package 'sw/device/tests' defined by /nightly/current_run/opentitan/sw/device/tests/BUILD
ERROR: no such target '//sw/device/tests:alert_handler_lpg_sleep_mode_alerts_test_sim_dv': target 'alert_handler_lpg_sleep_mode_alerts_test_sim_dv' not declared in package 'sw/device/tests' defined by /nightly/current_run/opentitan/sw/device/tests/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
|
|
| chip_sw_alert_handler_lpg_sleep_mode_pings | 23264830506709930516693202697161706113135542503676578278495766329584153702078 | None |
Use --verbose_failures to see the command lines of failed build steps.
ERROR: Analysis of target '//sw/device/tests:alert_handler_lpg_sleep_mode_pings_test_sim_dv' failed; build aborted: Target //sw/device/tests:alert_handler_lpg_sleep_mode_pings_test_sim_dv is incompatible and cannot be built, but was explicitly requested.
Dependency chain:
//sw/device/tests:alert_handler_lpg_sleep_mode_pings_test_sim_dv (b853eb) <-- target platform (//toolchain:opentitan_platform) didn't satisfy constraint @@platforms//:incompatible
INFO: Elapsed time: 0.316s, Critical Path: 0.03s
INFO: 1 process: 1 internal.
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
|
|
| chip_sw_alert_handler_lpg_clkoff | 17928110690507991945734888090224055789361714303210223014363242044122261061156 | None |
Use --verbose_failures to see the command lines of failed build steps.
ERROR: Analysis of target '//sw/device/tests:alert_handler_lpg_clkoff_test_sim_dv' failed; build aborted: Target //sw/device/tests:alert_handler_lpg_clkoff_test_sim_dv is incompatible and cannot be built, but was explicitly requested.
Dependency chain:
//sw/device/tests:alert_handler_lpg_clkoff_test_sim_dv (b853eb) <-- target platform (//toolchain:opentitan_platform) didn't satisfy constraint @@platforms//:incompatible
INFO: Elapsed time: 0.303s, Critical Path: 0.03s
INFO: 1 process: 1 internal.
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
|
|
| chip_sw_alert_handler_lpg_reset_toggle | 1718807056652290932416123168661645069257795540601742660186717471937630861779 | None |
Use --verbose_failures to see the command lines of failed build steps.
ERROR: Analysis of target '//sw/device/tests:alert_handler_lpg_reset_toggle_test_sim_dv' failed; build aborted: Target //sw/device/tests:alert_handler_lpg_reset_toggle_test_sim_dv is incompatible and cannot be built, but was explicitly requested.
Dependency chain:
//sw/device/tests:alert_handler_lpg_reset_toggle_test_sim_dv (b853eb) <-- target platform (//toolchain:opentitan_platform) didn't satisfy constraint @@platforms//:incompatible
INFO: Elapsed time: 0.291s, Critical Path: 0.03s
INFO: 1 process: 1 internal.
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
|
|
| chip_sw_alert_handler_entropy | 82543239740050380682605060314608152302664262912334996665556061987879183576966 | None |
Use --verbose_failures to see the command lines of failed build steps.
ERROR: Analysis of target '//sw/device/tests/sim_dv:alert_handler_entropy_test_sim_dv' failed; build aborted: Target //sw/device/tests/sim_dv:alert_handler_entropy_test_sim_dv is incompatible and cannot be built, but was explicitly requested.
Dependency chain:
//sw/device/tests/sim_dv:alert_handler_entropy_test_sim_dv (b853eb) <-- target platform (//toolchain:opentitan_platform) didn't satisfy constraint @@platforms//:incompatible
INFO: Elapsed time: 2.603s, Critical Path: 0.05s
INFO: 1 process: 1 internal.
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
|
|
| chip_sw_csrng_fuse_en_sw_app_read_test | 27801426865238636385379329047726480902025025421352180355349968568260684099234 | None |
Use --verbose_failures to see the command lines of failed build steps.
ERROR: Analysis of target '//sw/device/tests/sim_dv:csrng_fuse_en_sw_app_read_sim_dv' failed; build aborted: Target //sw/device/tests/sim_dv:csrng_fuse_en_sw_app_read_sim_dv is incompatible and cannot be built, but was explicitly requested.
Dependency chain:
//sw/device/tests/sim_dv:csrng_fuse_en_sw_app_read_sim_dv (b853eb) <-- target platform (//toolchain:opentitan_platform) didn't satisfy constraint @@platforms//:incompatible
INFO: Elapsed time: 0.813s, Critical Path: 0.03s
INFO: 1 process: 1 internal.
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
|
|
| chip_sw_kmac_app_rom | 96792529527630706395953797419085821108677096509336306818038055686769246713376 | None |
---- STDOUT ----
---- STDERR ----
WARNING: Build option --define has changed, discarding analysis cache (this can be expensive, see https://bazel.build/advanced/performance/iteration-speed).
DEBUG: /nightly/current_run/opentitan/rules/autogen.bzl:536:14: NOTE: stamping is disabled, the build_info section will use a fixed version string
ERROR: Error doing post analysis query: Evaluation of subquery "labels('data', //sw/device/tests:kmac_app_rom_test_sim_dv)" failed (did you want to use --keep_going?): in 'data' of rule //sw/device/tests:kmac_app_rom_test_sim_dv: configured target of type test_suite does not have attribute 'data'
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
|
|
| chip_sw_sram_ctrl_scrambled_access_jitter_en | 57121883157880958647521944716691473823231935284737810162379205401060668481327 | None |
---- STDOUT ----
---- STDERR ----
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/tests/sim_dv:sram_ctrl_scrambled_access_test_sim_dv': no such target '//sw/device/tests/sim_dv:sram_ctrl_scrambled_access_test_sim_dv': target 'sram_ctrl_scrambled_access_test_sim_dv' not declared in package 'sw/device/tests/sim_dv' defined by /nightly/current_run/opentitan/sw/device/tests/sim_dv/BUILD
ERROR: no such target '//sw/device/tests/sim_dv:sram_ctrl_scrambled_access_test_sim_dv': target 'sram_ctrl_scrambled_access_test_sim_dv' not declared in package 'sw/device/tests/sim_dv' defined by /nightly/current_run/opentitan/sw/device/tests/sim_dv/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
|
|
| chip_sw_sram_ctrl_execution_main | 50451619655880684557088457723365221291113514148438800908728498553228202058238 | None |
Use --verbose_failures to see the command lines of failed build steps.
ERROR: Analysis of target '//sw/device/tests/sim_dv:sram_ctrl_execution_main_test_sim_dv' failed; build aborted: Target //sw/device/tests/sim_dv:sram_ctrl_execution_main_test_sim_dv is incompatible and cannot be built, but was explicitly requested.
Dependency chain:
//sw/device/tests/sim_dv:sram_ctrl_execution_main_test_sim_dv (b853eb) <-- target platform (//toolchain:opentitan_platform) didn't satisfy constraint @@platforms//:incompatible
INFO: Elapsed time: 0.376s, Critical Path: 0.03s
INFO: 1 process: 1 internal.
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
|
|
| chip_sw_coremark | 45241758968256962755499300250467408434635243730394989386233692230534465832687 | None |
---- STDERR ----
WARNING: Target pattern parsing failed.
ERROR: Skipping '//third_party/coremark/top_darjeeling:coremark_test_sim_dv': no such package 'third_party/coremark/top_darjeeling': BUILD file not found in any of the following directories. Add a BUILD file to a directory to mark it as a package.
- third_party/coremark/top_darjeeling
ERROR: no such package 'third_party/coremark/top_darjeeling': BUILD file not found in any of the following directories. Add a BUILD file to a directory to mark it as a package.
- third_party/coremark/top_darjeeling
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
|
|
| chip_sw_clkmgr_reset_frequency | 78734781893276455031382312956598588243370686044781828449912356007333663856707 | None |
Use --verbose_failures to see the command lines of failed build steps.
ERROR: Analysis of target '//sw/device/tests:clkmgr_reset_frequency_test_sim_dv' failed; build aborted: Target //sw/device/tests:clkmgr_reset_frequency_test_sim_dv is incompatible and cannot be built, but was explicitly requested.
Dependency chain:
//sw/device/tests:clkmgr_reset_frequency_test_sim_dv (b853eb) <-- target platform (//toolchain:opentitan_platform) didn't satisfy constraint @@platforms//:incompatible
INFO: Elapsed time: 0.344s, Critical Path: 0.05s
INFO: 1 process: 1 internal.
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
|
|
| chip_sw_clkmgr_sleep_frequency | 18047829426649971488679526441606764433114424348583731508952004567567412712620 | None |
Use --verbose_failures to see the command lines of failed build steps.
ERROR: Analysis of target '//sw/device/tests:clkmgr_sleep_frequency_test_sim_dv' failed; build aborted: Target //sw/device/tests:clkmgr_sleep_frequency_test_sim_dv is incompatible and cannot be built, but was explicitly requested.
Dependency chain:
//sw/device/tests:clkmgr_sleep_frequency_test_sim_dv (b853eb) <-- target platform (//toolchain:opentitan_platform) didn't satisfy constraint @@platforms//:incompatible
INFO: Elapsed time: 0.370s, Critical Path: 0.02s
INFO: 1 process: 1 internal.
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
|
|
| chip_sw_ast_clk_outputs | 14459172769626750184477364236141056856167129909442130571990127731384858625809 | None |
Use --verbose_failures to see the command lines of failed build steps.
ERROR: Analysis of target '//sw/device/tests:ast_clk_outs_test_sim_dv' failed; build aborted: Target //sw/device/tests:ast_clk_outs_test_sim_dv is incompatible and cannot be built, but was explicitly requested.
Dependency chain:
//sw/device/tests:ast_clk_outs_test_sim_dv (b853eb) <-- target platform (//toolchain:opentitan_platform) didn't satisfy constraint @@platforms//:incompatible
INFO: Elapsed time: 0.324s, Critical Path: 0.03s
INFO: 1 process: 1 internal.
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
|
|
| chip_sw_lc_ctrl_program_error | 58145171798890620912097019485047565740239819927642089597894572386002226370177 | None |
Use --verbose_failures to see the command lines of failed build steps.
ERROR: Analysis of target '//sw/device/tests/sim_dv:lc_ctrl_program_error_sim_dv' failed; build aborted: Target //sw/device/tests/sim_dv:lc_ctrl_program_error_sim_dv is incompatible and cannot be built, but was explicitly requested.
Dependency chain:
//sw/device/tests/sim_dv:lc_ctrl_program_error_sim_dv (b853eb) <-- target platform (//toolchain:opentitan_platform) didn't satisfy constraint @@platforms//:incompatible
INFO: Elapsed time: 0.326s, Critical Path: 0.04s
INFO: 1 process: 1 internal.
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
|
|
| chip_sw_rv_dm_ndm_reset_req_when_cpu_halted | 38479225269010415745020406843996809105572324978285111548784223174356561275768 | None |
---- STDOUT ----
---- STDERR ----
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/tests:rv_dm_ndm_reset_req_when_cpu_halted_sim_dv': no such target '//sw/device/tests:rv_dm_ndm_reset_req_when_cpu_halted_sim_dv': target 'rv_dm_ndm_reset_req_when_cpu_halted_sim_dv' not declared in package 'sw/device/tests' defined by /nightly/current_run/opentitan/sw/device/tests/BUILD (did you mean rv_dm_ndm_reset_req_when_cpu_halted_dev_sim_dv, or rv_dm_ndm_reset_req_when_cpu_halted_rma_sim_dv?)
ERROR: no such target '//sw/device/tests:rv_dm_ndm_reset_req_when_cpu_halted_sim_dv': target 'rv_dm_ndm_reset_req_when_cpu_halted_sim_dv' not declared in package 'sw/device/tests' defined by /nightly/current_run/opentitan/sw/device/tests/BUILD (did you mean rv_dm_ndm_reset_req_when_cpu_halted_dev_sim_dv, or rv_dm_ndm_reset_req_when_cpu_halted_rma_sim_dv?)
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
|
|
| chip_sw_rv_dm_access_after_wakeup | 89088815337422270530780990682221840174813441688174635096273544503764602768283 | None |
---- STDOUT ----
---- STDERR ----
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/tests:rv_dm_access_after_wakeup_sim_dv': no such target '//sw/device/tests:rv_dm_access_after_wakeup_sim_dv': target 'rv_dm_access_after_wakeup_sim_dv' not declared in package 'sw/device/tests' defined by /nightly/current_run/opentitan/sw/device/tests/BUILD (did you mean rv_dm_access_after_wakeup_dev_sim_dv, or rv_dm_access_after_wakeup_rma_sim_dv?)
ERROR: no such target '//sw/device/tests:rv_dm_access_after_wakeup_sim_dv': target 'rv_dm_access_after_wakeup_sim_dv' not declared in package 'sw/device/tests' defined by /nightly/current_run/opentitan/sw/device/tests/BUILD (did you mean rv_dm_access_after_wakeup_dev_sim_dv, or rv_dm_access_after_wakeup_rma_sim_dv?)
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
|
|
| chip_sw_rv_dm_access_after_escalation_reset | 46318855615362384274048348240100582375899214192979792554194039936472545715969 | None |
Use --verbose_failures to see the command lines of failed build steps.
ERROR: Analysis of target '//sw/device/tests:alert_handler_escalation_test_sim_dv' failed; build aborted: Target //sw/device/tests:alert_handler_escalation_test_sim_dv is incompatible and cannot be built, but was explicitly requested.
Dependency chain:
//sw/device/tests:alert_handler_escalation_test_sim_dv (b853eb) <-- target platform (//toolchain:opentitan_platform) didn't satisfy constraint @@platforms//:incompatible
INFO: Elapsed time: 0.321s, Critical Path: 0.02s
INFO: 1 process: 1 internal.
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
|
|
| chip_sw_power_virus | 59831567298272127809728856656627984739251574234676073375787443907886290689404 | None |
Use --verbose_failures to see the command lines of failed build steps.
ERROR: Analysis of target '//sw/device/tests:power_virus_systemtest_sim_dv' failed; build aborted: Target //sw/device/tests:power_virus_systemtest_sim_dv is incompatible and cannot be built, but was explicitly requested.
Dependency chain:
//sw/device/tests:power_virus_systemtest_sim_dv (b853eb) <-- target platform (//toolchain:opentitan_platform) didn't satisfy constraint @@platforms//:incompatible
INFO: Elapsed time: 0.349s, Critical Path: 0.04s
INFO: 1 process: 1 internal.
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
|
|
| base_rom_e2e_smoke | 96201396636453210026243119691055550729570012665773138503611717766278968179682 | None |
_deploy_software_collateral(args)
~~~~~~~~~~~~~~~~~~~~~~~~~~~^^^^^^
File "/nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py", line 324, in _deploy_software_collateral
image_string = ImageString(image)
File "<string>", line 4, in __init__
File "/nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py", line 256, in __post_init__
assert flag in KNOWN_FLAGS, f"Unknown flag '{flag}' used in sw_image '{self.raw}'"
^^^^^^^^^^^^^^^^^^^
AssertionError: Unknown flag 'test_in_second_rom' used in sw_image '//sw/device/silicon_creator/rom/e2e:base_rom_e2e_smoke:7:test_in_second_rom'
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
|
|
| rom_e2e_smoke | 86024239398422996751690587182996102587748656356262993053187525670019983322875 | None |
---- STDOUT ----
---- STDERR ----
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_sim_dv': target 'empty_test_slot_a_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_sim_dv': target 'empty_test_slot_a_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
|
|
| rom_e2e_shutdown_exception_c | 90646353441333080192902851256875207949098053746873361090243766827860095441050 | None |
---- STDOUT ----
---- STDERR ----
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom:rom_with_fake_keys_sim_dv': no such target '//sw/device/silicon_creator/rom:rom_with_fake_keys_sim_dv': target 'rom_with_fake_keys_sim_dv' not declared in package 'sw/device/silicon_creator/rom' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom:rom_with_fake_keys_sim_dv': target 'rom_with_fake_keys_sim_dv' not declared in package 'sw/device/silicon_creator/rom' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
|
|
| rom_e2e_shutdown_output | 48548456935880569384522980985279263047798851442807981857786662205804509110397 | None |
---- STDOUT ----
---- STDERR ----
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_sim_dv': target 'empty_test_slot_a_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_sim_dv': target 'empty_test_slot_a_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
|
|
| rom_e2e_boot_policy_valid_a_good_b_good_test_unlocked0 | 37422664524520938529430010292346347052649565957863106932199300171254774015889 | None |
---- STDOUT ----
---- STDERR ----
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_sim_dv': target 'empty_test_slot_a_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_sim_dv': target 'empty_test_slot_a_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
|
|
| rom_e2e_boot_policy_valid_a_good_b_good_dev | 10767917748628607650518272214947547702846869764565527219902362813257920416767 | None |
---- STDOUT ----
---- STDERR ----
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_sim_dv': target 'empty_test_slot_a_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_sim_dv': target 'empty_test_slot_a_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
|
|
| rom_e2e_boot_policy_valid_a_good_b_good_prod | 70890183162323672290778935641365555709681243653291859102708603412502770969006 | None |
---- STDOUT ----
---- STDERR ----
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_sim_dv': target 'empty_test_slot_a_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_sim_dv': target 'empty_test_slot_a_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
|
|
| rom_e2e_boot_policy_valid_a_good_b_good_prod_end | 17917941825186861356755190505533678185865005253472627423508272382087588568711 | None |
---- STDOUT ----
---- STDERR ----
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_sim_dv': target 'empty_test_slot_a_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_sim_dv': target 'empty_test_slot_a_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
|
|
| rom_e2e_boot_policy_valid_a_good_b_good_rma | 103021544429065859198366579965608336590352790032861782037111182447908070316951 | None |
---- STDOUT ----
---- STDERR ----
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_sim_dv': target 'empty_test_slot_a_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_sim_dv': target 'empty_test_slot_a_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
|
|
| rom_e2e_boot_policy_valid_a_good_b_bad_test_unlocked0 | 58766033079434154267925980559929364928207306662541351931430305029506928667317 | None |
---- STDOUT ----
---- STDERR ----
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_sim_dv': target 'empty_test_slot_a_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_sim_dv': target 'empty_test_slot_a_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
|
|
| rom_e2e_boot_policy_valid_a_good_b_bad_dev | 50746753381205802284609785933463152366952510523056615303478766562648286715138 | None |
---- STDOUT ----
---- STDERR ----
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_sim_dv': target 'empty_test_slot_a_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_sim_dv': target 'empty_test_slot_a_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
|
|
| rom_e2e_boot_policy_valid_a_good_b_bad_prod | 79438510002365791312743318345189755681137404580638177787338099708646945037969 | None |
---- STDOUT ----
---- STDERR ----
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_sim_dv': target 'empty_test_slot_a_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_sim_dv': target 'empty_test_slot_a_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
|
|
| rom_e2e_boot_policy_valid_a_good_b_bad_prod_end | 88759542515732626927045620579686571123923943318812239888512371762192834342365 | None |
---- STDOUT ----
---- STDERR ----
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_sim_dv': target 'empty_test_slot_a_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_sim_dv': target 'empty_test_slot_a_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
|
|
| rom_e2e_boot_policy_valid_a_good_b_bad_rma | 12694979756183594633455190619058011364423991003591186618746712993770765507623 | None |
---- STDOUT ----
---- STDERR ----
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_sim_dv': target 'empty_test_slot_a_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_sim_dv': target 'empty_test_slot_a_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
|
|
| rom_e2e_boot_policy_valid_a_bad_b_good_test_unlocked0 | 94143320998104349173335864773126811716121456016729695795727320002397286338594 | None |
---- STDERR ----
Another command (pid=600296) is running. Waiting for it to complete on the server (server_pid=65989)...
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_b_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_b_sim_dv': target 'empty_test_slot_b_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_b_sim_dv': target 'empty_test_slot_b_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
|
|
| rom_e2e_boot_policy_valid_a_bad_b_good_dev | 15313222257179740909430595821275941112723761326752514211624649203805411660774 | None |
---- STDERR ----
Another command (pid=600046) is running. Waiting for it to complete on the server (server_pid=65989)...
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_b_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_b_sim_dv': target 'empty_test_slot_b_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_b_sim_dv': target 'empty_test_slot_b_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
|
|
| rom_e2e_boot_policy_valid_a_bad_b_good_prod | 65800369100428923843285439578414642388494238973301644881838584613031648871997 | None |
---- STDOUT ----
---- STDERR ----
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_b_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_b_sim_dv': target 'empty_test_slot_b_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_b_sim_dv': target 'empty_test_slot_b_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
|
|
| rom_e2e_boot_policy_valid_a_bad_b_good_prod_end | 69064589940768829025897150685398486430974164044505518868515690699226072274029 | None |
---- STDOUT ----
---- STDERR ----
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_b_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_b_sim_dv': target 'empty_test_slot_b_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_b_sim_dv': target 'empty_test_slot_b_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
|
|
| rom_e2e_boot_policy_valid_a_bad_b_good_rma | 34747596378341641559755726726477807147228452340370311177915840585513150912759 | None |
---- STDOUT ----
---- STDERR ----
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_b_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_b_sim_dv': target 'empty_test_slot_b_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_b_sim_dv': target 'empty_test_slot_b_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
|
|
| rom_e2e_sigverify_always_a_bad_b_bad_test_unlocked0 | 87787511167737766242816944146487087036938236513539745130821083173745511256679 | None |
---- STDOUT ----
---- STDERR ----
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:otp_img_sigverify_always_test_unlocked0': no such target '//sw/device/silicon_creator/rom/e2e:otp_img_sigverify_always_test_unlocked0': target 'otp_img_sigverify_always_test_unlocked0' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:otp_img_sigverify_always_test_unlocked0': target 'otp_img_sigverify_always_test_unlocked0' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
|
|
| rom_e2e_sigverify_always_a_bad_b_bad_dev | 32588447148525405365889866064382672715224323812599114920484311895612816713828 | None |
---- STDOUT ----
---- STDERR ----
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:otp_img_sigverify_always_dev': no such target '//sw/device/silicon_creator/rom/e2e:otp_img_sigverify_always_dev': target 'otp_img_sigverify_always_dev' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:otp_img_sigverify_always_dev': target 'otp_img_sigverify_always_dev' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
|
|
| rom_e2e_sigverify_always_a_bad_b_bad_prod | 51379302580640768658292225993879918326049674896496959104659785790974997041685 | None |
---- STDOUT ----
---- STDERR ----
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:otp_img_sigverify_always_prod': no such target '//sw/device/silicon_creator/rom/e2e:otp_img_sigverify_always_prod': target 'otp_img_sigverify_always_prod' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:otp_img_sigverify_always_prod': target 'otp_img_sigverify_always_prod' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
|
|
| rom_e2e_sigverify_always_a_bad_b_bad_prod_end | 97699633414327154931076325149691139372980077710889916135505760037694513503645 | None |
---- STDOUT ----
---- STDERR ----
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:otp_img_sigverify_always_prod_end': no such target '//sw/device/silicon_creator/rom/e2e:otp_img_sigverify_always_prod_end': target 'otp_img_sigverify_always_prod_end' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:otp_img_sigverify_always_prod_end': target 'otp_img_sigverify_always_prod_end' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
|
|
| rom_e2e_sigverify_always_a_bad_b_bad_rma | 28142639115232727802003495107390567033070256902737390845575341770631745484286 | None |
---- STDOUT ----
---- STDERR ----
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:otp_img_sigverify_always_rma': no such target '//sw/device/silicon_creator/rom/e2e:otp_img_sigverify_always_rma': target 'otp_img_sigverify_always_rma' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:otp_img_sigverify_always_rma': target 'otp_img_sigverify_always_rma' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
|
|
| rom_e2e_sigverify_always_a_bad_b_nothing_test_unlocked0 | 77877473296973526484916526260119044110412399707371412244208821731232732079395 | None |
---- STDOUT ----
---- STDERR ----
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:otp_img_sigverify_always_test_unlocked0': no such target '//sw/device/silicon_creator/rom/e2e:otp_img_sigverify_always_test_unlocked0': target 'otp_img_sigverify_always_test_unlocked0' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:otp_img_sigverify_always_test_unlocked0': target 'otp_img_sigverify_always_test_unlocked0' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
|
|
| rom_e2e_sigverify_always_a_bad_b_nothing_dev | 47508794047619796004016360737826747024824263178829809546209733073308437982066 | None |
---- STDOUT ----
---- STDERR ----
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:otp_img_sigverify_always_dev': no such target '//sw/device/silicon_creator/rom/e2e:otp_img_sigverify_always_dev': target 'otp_img_sigverify_always_dev' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:otp_img_sigverify_always_dev': target 'otp_img_sigverify_always_dev' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
|
|
| rom_e2e_sigverify_always_a_bad_b_nothing_prod | 104090069477044291536885534982737747113741210330503971985820105150068514163743 | None |
---- STDOUT ----
---- STDERR ----
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:otp_img_sigverify_always_prod': no such target '//sw/device/silicon_creator/rom/e2e:otp_img_sigverify_always_prod': target 'otp_img_sigverify_always_prod' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:otp_img_sigverify_always_prod': target 'otp_img_sigverify_always_prod' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
|
|
| rom_e2e_sigverify_always_a_bad_b_nothing_prod_end | 60032908165346661631524006478111592185757875579690037122814072520748589242883 | None |
---- STDOUT ----
---- STDERR ----
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:otp_img_sigverify_always_prod_end': no such target '//sw/device/silicon_creator/rom/e2e:otp_img_sigverify_always_prod_end': target 'otp_img_sigverify_always_prod_end' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:otp_img_sigverify_always_prod_end': target 'otp_img_sigverify_always_prod_end' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
|
|
| rom_e2e_sigverify_always_a_bad_b_nothing_rma | 1670397971268340777431987509037355204060374040757391607784026740268544344307 | None |
---- STDOUT ----
---- STDERR ----
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:otp_img_sigverify_always_rma': no such target '//sw/device/silicon_creator/rom/e2e:otp_img_sigverify_always_rma': target 'otp_img_sigverify_always_rma' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:otp_img_sigverify_always_rma': target 'otp_img_sigverify_always_rma' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
|
|
| rom_e2e_sigverify_always_a_nothing_b_bad_test_unlocked0 | 90791739611047721947594879581412674171477181114308538160765463615136513933366 | None |
---- STDOUT ----
---- STDERR ----
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:otp_img_sigverify_always_test_unlocked0': no such target '//sw/device/silicon_creator/rom/e2e:otp_img_sigverify_always_test_unlocked0': target 'otp_img_sigverify_always_test_unlocked0' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:otp_img_sigverify_always_test_unlocked0': target 'otp_img_sigverify_always_test_unlocked0' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
|
|
| rom_e2e_sigverify_always_a_nothing_b_bad_dev | 29458317738143733855619633689954661836445416168894495249133144338912351932515 | None |
---- STDOUT ----
---- STDERR ----
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:otp_img_sigverify_always_dev': no such target '//sw/device/silicon_creator/rom/e2e:otp_img_sigverify_always_dev': target 'otp_img_sigverify_always_dev' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:otp_img_sigverify_always_dev': target 'otp_img_sigverify_always_dev' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
|
|
| rom_e2e_sigverify_always_a_nothing_b_bad_prod | 67973978748771310007236850245845982955856718189745047541829599145007628577846 | None |
---- STDOUT ----
---- STDERR ----
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:otp_img_sigverify_always_prod': no such target '//sw/device/silicon_creator/rom/e2e:otp_img_sigverify_always_prod': target 'otp_img_sigverify_always_prod' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:otp_img_sigverify_always_prod': target 'otp_img_sigverify_always_prod' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
|
|
| rom_e2e_sigverify_always_a_nothing_b_bad_prod_end | 86674268330655361960707651897607188494405419608399771022931893254817976394345 | None |
---- STDERR ----
Another command (pid=611277) is running. Waiting for it to complete on the server (server_pid=65989)...
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:otp_img_sigverify_always_prod_end': no such target '//sw/device/silicon_creator/rom/e2e:otp_img_sigverify_always_prod_end': target 'otp_img_sigverify_always_prod_end' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:otp_img_sigverify_always_prod_end': target 'otp_img_sigverify_always_prod_end' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
|
|
| rom_e2e_sigverify_always_a_nothing_b_bad_rma | 108261576349354606965723105279140338059371513828764519746279173420727113761720 | None |
---- STDERR ----
Another command (pid=610846) is running. Waiting for it to complete on the server (server_pid=65989)...
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:otp_img_sigverify_always_rma': no such target '//sw/device/silicon_creator/rom/e2e:otp_img_sigverify_always_rma': target 'otp_img_sigverify_always_rma' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:otp_img_sigverify_always_rma': target 'otp_img_sigverify_always_rma' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
|
|
| rom_e2e_asm_init_test_unlocked0 | 33426432239160894453840397110152550287234376184389769281552668532352635375907 | None |
---- STDOUT ----
---- STDERR ----
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_sim_dv': target 'empty_test_slot_a_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_sim_dv': target 'empty_test_slot_a_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
|
|
| rom_e2e_asm_init_dev | 10303280808836042209168664734167240473560657743459253591084198567572586184387 | None |
---- STDOUT ----
---- STDERR ----
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_sim_dv': target 'empty_test_slot_a_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_sim_dv': target 'empty_test_slot_a_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
|
|
| rom_e2e_asm_init_prod | 81223463778133315914781303469813778101356837433186069998827633627157430310695 | None |
---- STDOUT ----
---- STDERR ----
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_sim_dv': target 'empty_test_slot_a_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_sim_dv': target 'empty_test_slot_a_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
|
|
| rom_e2e_asm_init_prod_end | 74877926964710064269652784198556220921109031921215992628207225859677784336796 | None |
---- STDOUT ----
---- STDERR ----
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_sim_dv': target 'empty_test_slot_a_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_sim_dv': target 'empty_test_slot_a_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
|
|
| rom_e2e_asm_init_rma | 103874254496030266756149532056058675612196381795154479577276893872621991266490 | None |
---- STDOUT ----
---- STDERR ----
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_sim_dv': target 'empty_test_slot_a_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_sim_dv': target 'empty_test_slot_a_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
|
|
| rom_e2e_jtag_debug_test_unlocked0 | 75471042633444795620872918324937537455249849858168784038666330111537021743663 | None |
---- STDOUT ----
---- STDERR ----
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:img_test_unlocked0_exec_disabled': no such target '//sw/device/silicon_creator/rom/e2e:img_test_unlocked0_exec_disabled': target 'img_test_unlocked0_exec_disabled' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:img_test_unlocked0_exec_disabled': target 'img_test_unlocked0_exec_disabled' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
|
|
| rom_e2e_jtag_debug_dev | 19077035917240621262375376519115905909168147437835406891346573840319571550730 | None |
---- STDOUT ----
---- STDERR ----
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:img_dev_exec_disabled': no such target '//sw/device/silicon_creator/rom/e2e:img_dev_exec_disabled': target 'img_dev_exec_disabled' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:img_dev_exec_disabled': target 'img_dev_exec_disabled' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
|
|
| rom_e2e_jtag_debug_rma | 16386353145182568374656418600377915716455355902946611806292121640534369683184 | None |
---- STDOUT ----
---- STDERR ----
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:img_rma_exec_disabled': no such target '//sw/device/silicon_creator/rom/e2e:img_rma_exec_disabled': target 'img_rma_exec_disabled' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:img_rma_exec_disabled': target 'img_rma_exec_disabled' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
|
|
| rom_e2e_jtag_inject_test_unlocked0 | 40212600522978026576993698807341331966444814636718376164400500848244319412104 | None |
---- STDOUT ----
---- STDERR ----
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:img_dev_exec_disabled': no such target '//sw/device/silicon_creator/rom/e2e:img_dev_exec_disabled': target 'img_dev_exec_disabled' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:img_dev_exec_disabled': target 'img_dev_exec_disabled' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
|
|
| rom_e2e_jtag_inject_dev | 43669399822787461020922966722103002523517886044137434531257416010708142828471 | None |
---- STDOUT ----
---- STDERR ----
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:img_dev_exec_disabled': no such target '//sw/device/silicon_creator/rom/e2e:img_dev_exec_disabled': target 'img_dev_exec_disabled' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:img_dev_exec_disabled': target 'img_dev_exec_disabled' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
|
|
| rom_e2e_jtag_inject_rma | 106165175725587000186061538430737122787917408038769047267234419700964234249655 | None |
---- STDOUT ----
---- STDERR ----
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:img_dev_exec_disabled': no such target '//sw/device/silicon_creator/rom/e2e:img_dev_exec_disabled': target 'img_dev_exec_disabled' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:img_dev_exec_disabled': target 'img_dev_exec_disabled' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
|
|
| rom_e2e_static_critical | 106012893488807409206599946654060304717495372633881210887176600766500138734586 | None |
---- STDOUT ----
---- STDERR ----
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom:rom_with_fake_keys_sim_dv': no such target '//sw/device/silicon_creator/rom:rom_with_fake_keys_sim_dv': target 'rom_with_fake_keys_sim_dv' not declared in package 'sw/device/silicon_creator/rom' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom:rom_with_fake_keys_sim_dv': target 'rom_with_fake_keys_sim_dv' not declared in package 'sw/device/silicon_creator/rom' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
|
|
| rom_e2e_keymgr_init_rom_ext_meas | 87606453538114313318337256765446115041046216797518438712188091899570901849374 | None |
---- STDOUT ----
---- STDERR ----
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:rom_e2e_keymgr_init_test_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:rom_e2e_keymgr_init_test_sim_dv': target 'rom_e2e_keymgr_init_test_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:rom_e2e_keymgr_init_test_sim_dv': target 'rom_e2e_keymgr_init_test_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
|
|
| rom_e2e_keymgr_init_rom_ext_no_meas | 70292998468962677121176478356029950491971399169245966290860647449081257301412 | None |
---- STDOUT ----
---- STDERR ----
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:rom_e2e_keymgr_init_test_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:rom_e2e_keymgr_init_test_sim_dv': target 'rom_e2e_keymgr_init_test_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:rom_e2e_keymgr_init_test_sim_dv': target 'rom_e2e_keymgr_init_test_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
|
|
| rom_e2e_keymgr_init_rom_ext_invalid_meas | 110983841394150754277250301447011821109442772235690472464898802682324277474560 | None |
---- STDOUT ----
---- STDERR ----
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:rom_e2e_keymgr_init_test_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:rom_e2e_keymgr_init_test_sim_dv': target 'rom_e2e_keymgr_init_test_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:rom_e2e_keymgr_init_test_sim_dv': target 'rom_e2e_keymgr_init_test_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
|
|
| rom_e2e_sigverify_mod_exp_test_unlocked0_otbn | 35900082598730836323983900038292241348852742418459752429146284438210446791536 | None |
---- STDOUT ----
---- STDERR ----
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_sigverify_mod_exp_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_sigverify_mod_exp_sim_dv': target 'empty_test_sigverify_mod_exp_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_sigverify_mod_exp_sim_dv': target 'empty_test_sigverify_mod_exp_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
|
|
| rom_e2e_sigverify_mod_exp_test_unlocked0_sw | 93753064840320593578025725396083332809442881364760666752941858453406772733122 | None |
---- STDOUT ----
---- STDERR ----
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_sigverify_mod_exp_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_sigverify_mod_exp_sim_dv': target 'empty_test_sigverify_mod_exp_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_sigverify_mod_exp_sim_dv': target 'empty_test_sigverify_mod_exp_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
|
|
| rom_e2e_sigverify_mod_exp_dev_otbn | 71876524240799615529414136627252688991097497204634354940020232692769611116546 | None |
---- STDOUT ----
---- STDERR ----
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_sigverify_mod_exp_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_sigverify_mod_exp_sim_dv': target 'empty_test_sigverify_mod_exp_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_sigverify_mod_exp_sim_dv': target 'empty_test_sigverify_mod_exp_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
|
|
| rom_e2e_sigverify_mod_exp_dev_sw | 69722073371685111322806968230752915575979197579459282787487396605588450347144 | None |
---- STDOUT ----
---- STDERR ----
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_sigverify_mod_exp_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_sigverify_mod_exp_sim_dv': target 'empty_test_sigverify_mod_exp_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_sigverify_mod_exp_sim_dv': target 'empty_test_sigverify_mod_exp_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
|
|
| rom_e2e_sigverify_mod_exp_prod_otbn | 42374303926431409285038769257173569937413327472886220151560435867866921719882 | None |
---- STDOUT ----
---- STDERR ----
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_sigverify_mod_exp_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_sigverify_mod_exp_sim_dv': target 'empty_test_sigverify_mod_exp_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_sigverify_mod_exp_sim_dv': target 'empty_test_sigverify_mod_exp_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
|
|
| rom_e2e_sigverify_mod_exp_prod_sw | 46327738524685810958362976752369144619720903934052684059445435217702668162519 | None |
---- STDOUT ----
---- STDERR ----
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_sigverify_mod_exp_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_sigverify_mod_exp_sim_dv': target 'empty_test_sigverify_mod_exp_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_sigverify_mod_exp_sim_dv': target 'empty_test_sigverify_mod_exp_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
|
|
| rom_e2e_sigverify_mod_exp_prod_end_otbn | 13650623485822454180409674561336887139028844216881570460953332076844226163954 | None |
---- STDOUT ----
---- STDERR ----
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_sigverify_mod_exp_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_sigverify_mod_exp_sim_dv': target 'empty_test_sigverify_mod_exp_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_sigverify_mod_exp_sim_dv': target 'empty_test_sigverify_mod_exp_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
|
|
| rom_e2e_sigverify_mod_exp_prod_end_sw | 97792825837742494445466251974419769229367121312170586320499641063129655695697 | None |
---- STDOUT ----
---- STDERR ----
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_sigverify_mod_exp_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_sigverify_mod_exp_sim_dv': target 'empty_test_sigverify_mod_exp_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_sigverify_mod_exp_sim_dv': target 'empty_test_sigverify_mod_exp_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
|
|
| rom_e2e_sigverify_mod_exp_rma_otbn | 2281438376081072088249312932705009531633415102163515202311363068889311061065 | None |
---- STDOUT ----
---- STDERR ----
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_sigverify_mod_exp_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_sigverify_mod_exp_sim_dv': target 'empty_test_sigverify_mod_exp_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_sigverify_mod_exp_sim_dv': target 'empty_test_sigverify_mod_exp_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
|
|
| rom_e2e_sigverify_mod_exp_rma_sw | 38358377538814282660210684227677559638369241411687021685279963194740439965178 | None |
---- STDOUT ----
---- STDERR ----
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_sigverify_mod_exp_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_sigverify_mod_exp_sim_dv': target 'empty_test_sigverify_mod_exp_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_sigverify_mod_exp_sim_dv': target 'empty_test_sigverify_mod_exp_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
|
|
| rom_volatile_raw_unlock | 18027053249172162051839542904313586917195960636585338233185906845972899988265 | None |
---- STDOUT ----
---- STDERR ----
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_sim_dv': target 'empty_test_slot_a_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_sim_dv': target 'empty_test_slot_a_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
|
|
| rom_raw_unlock | 17401933006597739721091271208338446903535235256910152049317988546568324697914 | None |
---- STDOUT ----
---- STDERR ----
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_sim_dv': target 'empty_test_slot_a_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_sim_dv': target 'empty_test_slot_a_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
|
|
| rom_e2e_self_hash | 35583169157164705428392933761857404210358602650323943316315181700451189622865 | None |
---- STDERR ----
Another command (pid=620007) is running. Waiting for it to complete on the server (server_pid=65989)...
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:otp_img_sigverify_mod_exp_rma_otbn': no such target '//sw/device/silicon_creator/rom/e2e:otp_img_sigverify_mod_exp_rma_otbn': target 'otp_img_sigverify_mod_exp_rma_otbn' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:otp_img_sigverify_mod_exp_rma_otbn': target 'otp_img_sigverify_mod_exp_rma_otbn' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
|
|
| chip_sw_uart_smoketest_signed | 49258333532754648714826507987754581752484204155362155904949061272190713705210 | None |
---- STDOUT ----
---- STDERR ----
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/tests:uart_smoketest_signed_sim_dv': no such target '//sw/device/tests:uart_smoketest_signed_sim_dv': target 'uart_smoketest_signed_sim_dv' not declared in package 'sw/device/tests' defined by /nightly/current_run/opentitan/sw/device/tests/BUILD
ERROR: no such target '//sw/device/tests:uart_smoketest_signed_sim_dv': target 'uart_smoketest_signed_sim_dv' not declared in package 'sw/device/tests' defined by /nightly/current_run/opentitan/sw/device/tests/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
|
|
| rom_keymgr_functest | 41131295510969652505466943897130523211635059801287637111501771716555737556002 | None |
Use --verbose_failures to see the command lines of failed build steps.
ERROR: Analysis of target '//sw/device/silicon_creator/lib/drivers:keymgr_functest_sim_dv' failed; build aborted: Target //sw/device/silicon_creator/lib/drivers:keymgr_functest_sim_dv is incompatible and cannot be built, but was explicitly requested.
Dependency chain:
//sw/device/silicon_creator/lib/drivers:keymgr_functest_sim_dv (b853eb) <-- target platform (//toolchain:opentitan_platform) didn't satisfy constraint @@platforms//:incompatible
INFO: Elapsed time: 1.477s, Critical Path: 0.05s
INFO: 1 process: 1 internal.
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
|
|
| xmsim: *E,ASRTST (/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-xcelium/default/fusesoc-work/src/lowrisc_ip_lc_ctrl_*/rtl/lc_ctrl.sv,885): (time * NS) Assertion LcInitDoneSticky_A has failed (* cycles, starting * NS) | ||||
| chip_sw_all_escalation_resets | 55081474452021901130808606086773645439194995369066977366010840299901704782177 | 302 |
xmsim: *E,ASRTST (/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-xcelium/default/fusesoc-work/src/lowrisc_ip_lc_ctrl_0.1/rtl/lc_ctrl.sv,885): (time 180078 NS) Assertion tb.dut.top_darjeeling.u_lc_ctrl.LcInitDoneSticky_A has failed (2 cycles, starting 180074 NS)
UVM_ERROR @ 180.078000 us: (lc_ctrl.sv:885) [ASSERT FAILED] LcInitDoneSticky_A
UVM_INFO @ 180.078000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| chip_sw_otp_ctrl_escalation | 60789008710833258465229453486875676569411198452349339277636648646019285152056 | 301 |
xmsim: *E,ASRTST (/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-xcelium/default/fusesoc-work/src/lowrisc_ip_lc_ctrl_0.1/rtl/lc_ctrl.sv,885): (time 180158 NS) Assertion tb.dut.top_darjeeling.u_lc_ctrl.LcInitDoneSticky_A has failed (2 cycles, starting 180154 NS)
UVM_ERROR @ 180.158000 us: (lc_ctrl.sv:885) [ASSERT FAILED] LcInitDoneSticky_A
UVM_INFO @ 180.158000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| Job timed out after * minutes | ||||
| chip_sw_rstmgr_rst_cnsty_escalation | 96195601349184850635052542518893531823404619096003771987323336517832443287643 | None |
Job timed out after 60 minutes
|
|
| chip_sw_spi_device_pass_through | 27815251364384955033545799336288087509565334202668381309731310843652103435929 | None |
Job timed out after 60 minutes
|
|
| chip_sw_rom_ctrl_integrity_check | 104415272380165996209404764591149653286992558186619985354109282612451269953084 | None |
Job timed out after 60 minutes
|
|
| UVM_ERROR @ * us: (sw_logger_if.sv:526) [spi_passthrough_test_sim_dv(sw/device/tests/sim_dv/spi_passthrough_test.c:382)] CHECK-fail: irq == kDtSpiDeviceIrqUploadCmdfifoNotEmpty | ||||
| chip_sw_spi_device_pass_through_collision | 421290350835719709338182847183386309387266900342217721918440252852255189701 | 302 |
UVM_ERROR @ 306.663500 us: (sw_logger_if.sv:526) [spi_passthrough_test_sim_dv(sw/device/tests/sim_dv/spi_passthrough_test.c:382)] CHECK-fail: irq == kDtSpiDeviceIrqUploadCmdfifoNotEmpty
UVM_INFO @ 306.663500 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| UVM_ERROR @ * us: (sw_logger_if.sv:526) [rstmgr_alert_info_test_sim_dv(sw/device/lib/testing/alert_handler_testutils.c:78)] CHECK-fail: word_index < dump_size | ||||
| chip_sw_rstmgr_alert_info | 82194089138344310202822382287885295215241679934863572696083565409960696105315 | 314 |
UVM_ERROR @ 334.791500 us: (sw_logger_if.sv:526) [rstmgr_alert_info_test_sim_dv(sw/device/lib/testing/alert_handler_testutils.c:78)] CHECK-fail: word_index < dump_size
UVM_INFO @ 334.791500 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| xmsim: *E,ASRTST (/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-xcelium/default/fusesoc-work/src/lowrisc_darjeeling_dv_pwrmgr_sva_*/pwrmgr_rstreqs_sva_if.sv,59): (time * NS) Assertion HwResetOff_A has failed (* cycles, starting * NS) | ||||
| chip_sw_rstmgr_cpu_info | 107625700409629161133159607593210993927831636016993447055992296716154185767493 | 319 |
xmsim: *E,ASRTST (/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-xcelium/default/fusesoc-work/src/lowrisc_darjeeling_dv_pwrmgr_sva_0.1/pwrmgr_rstreqs_sva_if.sv,59): (time 413096 NS) Assertion tb.dut.top_darjeeling.pwrmgr_rstreqs_sva_if.gen_hw_resets[0].HwResetOff_A has failed (401 cycles, starting 406696 NS)
UVM_ERROR @ 413.096000 us: (pwrmgr_rstreqs_sva_if.sv:59) [ASSERT FAILED] HwResetOff_A
UVM_INFO @ 413.096000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| chip_sw_clkmgr_off_aes_trans | 29286450073079231239620349707497373309285588619703642250898485083572749933896 | 296 |
xmsim: *E,ASRTST (/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-xcelium/default/fusesoc-work/src/lowrisc_darjeeling_dv_pwrmgr_sva_0.1/pwrmgr_rstreqs_sva_if.sv,59): (time 184552 NS) Assertion tb.dut.top_darjeeling.pwrmgr_rstreqs_sva_if.gen_hw_resets[0].HwResetOff_A has failed (401 cycles, starting 178152 NS)
UVM_ERROR @ 184.552000 us: (pwrmgr_rstreqs_sva_if.sv:59) [ASSERT FAILED] HwResetOff_A
UVM_INFO @ 184.552000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| chip_sw_clkmgr_off_hmac_trans | 33636164156634169945769157755749458462135085139483844847244707429005292337169 | 296 |
xmsim: *E,ASRTST (/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-xcelium/default/fusesoc-work/src/lowrisc_darjeeling_dv_pwrmgr_sva_0.1/pwrmgr_rstreqs_sva_if.sv,59): (time 184648 NS) Assertion tb.dut.top_darjeeling.pwrmgr_rstreqs_sva_if.gen_hw_resets[0].HwResetOff_A has failed (401 cycles, starting 178248 NS)
UVM_ERROR @ 184.648000 us: (pwrmgr_rstreqs_sva_if.sv:59) [ASSERT FAILED] HwResetOff_A
UVM_INFO @ 184.648000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| chip_sw_clkmgr_off_kmac_trans | 553610824270352837256536513445238001566288185701202010424753292532827296862 | 296 |
xmsim: *E,ASRTST (/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-xcelium/default/fusesoc-work/src/lowrisc_darjeeling_dv_pwrmgr_sva_0.1/pwrmgr_rstreqs_sva_if.sv,59): (time 184520 NS) Assertion tb.dut.top_darjeeling.pwrmgr_rstreqs_sva_if.gen_hw_resets[0].HwResetOff_A has failed (401 cycles, starting 178120 NS)
UVM_ERROR @ 184.520000 us: (pwrmgr_rstreqs_sva_if.sv:59) [ASSERT FAILED] HwResetOff_A
UVM_INFO @ 184.520000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| chip_sw_clkmgr_off_otbn_trans | 21403028123723596759979504649781419559284579684861314019395343755656888203297 | 296 |
xmsim: *E,ASRTST (/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-xcelium/default/fusesoc-work/src/lowrisc_darjeeling_dv_pwrmgr_sva_0.1/pwrmgr_rstreqs_sva_if.sv,59): (time 184536 NS) Assertion tb.dut.top_darjeeling.pwrmgr_rstreqs_sva_if.gen_hw_resets[0].HwResetOff_A has failed (401 cycles, starting 178136 NS)
UVM_ERROR @ 184.536000 us: (pwrmgr_rstreqs_sva_if.sv:59) [ASSERT FAILED] HwResetOff_A
UVM_INFO @ 184.536000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| UVM_ERROR @ * us: (chip_sw_soc_proxy_smoke_vseq.sv:58) [chip_env_pkg::chip_sw_soc_proxy_smoke_vseq.body] Resets did not complete within required time! | ||||
| chip_sw_soc_proxy_smoketest | 51834756222493657428857203368857634204948071766063754393526789612675845255203 | 293 |
UVM_ERROR @ 157.272000 us: (chip_sw_soc_proxy_smoke_vseq.sv:58) [chip_env_pkg::chip_sw_soc_proxy_smoke_vseq.body] Resets did not complete within required time!
UVM_INFO @ 157.272000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| UVM_ERROR @ * us: (sw_logger_if.sv:526) [soc_proxy_external_wakeup_sim_dv(sw/device/tests/soc_proxy_external_wakeup.c:50)] DIF-fail: dif_pwrmgr_get_request_sources(&pwrmgr, kDifPwrmgrReqTypeWakeup, &wakeup_req_srcs) returns * | ||||
| chip_sw_soc_proxy_external_wakeup | 52342956009734618942113373650274510335554240835021768460625112856265051374137 | 291 |
UVM_ERROR @ 157.631500 us: (sw_logger_if.sv:526) [soc_proxy_external_wakeup_sim_dv(sw/device/tests/soc_proxy_external_wakeup.c:50)] DIF-fail: dif_pwrmgr_get_request_sources(&pwrmgr, kDifPwrmgrReqTypeWakeup, &wakeup_req_srcs) returns 3
UVM_INFO @ 157.631500 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| UVM_ERROR @ * us: (sw_logger_if.sv:526) [aon_timer_irq_test_sim_dv(sw/device/tests/aon_timer_irq_test.c:139)] CHECK-fail: Timer took * usec which is not in the range * usec and * usec | ||||
| chip_sw_aon_timer_irq | 19367104178975034851608692648099994268656087742456649115300391206360211755653 | 292 |
UVM_ERROR @ 520.509500 us: (sw_logger_if.sv:526) [aon_timer_irq_test_sim_dv(sw/device/tests/aon_timer_irq_test.c:139)] CHECK-fail: Timer took 3585 usec which is not in the range 327 usec and 376 usec
UVM_INFO @ 520.509500 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| UVM_ERROR @ * us: (sw_logger_if.sv:526) [aon_timer_wdog_bite_reset_test_sim_dv(sw/device/tests/aon_timer_wdog_bite_reset_test.c:84)] CHECK-fail: Wdog bark irq did not rise after * microseconds | ||||
| chip_sw_aon_timer_wdog_bite_reset | 95452182390758961375878306836509363148301232064166014804901839407017937677260 | 293 |
UVM_ERROR @ 183.223500 us: (sw_logger_if.sv:526) [aon_timer_wdog_bite_reset_test_sim_dv(sw/device/tests/aon_timer_wdog_bite_reset_test.c:84)] CHECK-fail: Wdog bark irq did not rise after 201 microseconds
UVM_INFO @ 183.223500 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| UVM_FATAL @ * us: (dv_utils_pkg.sv:266) [dv_utils_pkg::sw_symbol_get_addr_size.unmblk2] Check failed (ret) Failed to read line from "kJitterEnabled.dat" | ||||
| chip_sw_otbn_ecdsa_op_irq_jitter_en | 41544318558992363901097333390333752746843491693672260280122908366257480575571 | 284 |
UVM_FATAL @ 10.260001 us: (dv_utils_pkg.sv:266) [dv_utils_pkg::sw_symbol_get_addr_size.unmblk2] Check failed (ret) Failed to read line from "kJitterEnabled.dat"
UVM_INFO @ 10.260001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| chip_sw_aes_enc_jitter_en | 60084779665500549224568775071402459306705212389805613004496540108482780253177 | 284 |
UVM_FATAL @ 10.380001 us: (dv_utils_pkg.sv:266) [dv_utils_pkg::sw_symbol_get_addr_size.unmblk2] Check failed (ret) Failed to read line from "kJitterEnabled.dat"
UVM_INFO @ 10.380001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| chip_sw_hmac_enc_jitter_en | 98492791363346989125354156678553937306297992224708446826553609725853708346305 | 284 |
UVM_FATAL @ 10.380001 us: (dv_utils_pkg.sv:266) [dv_utils_pkg::sw_symbol_get_addr_size.unmblk2] Check failed (ret) Failed to read line from "kJitterEnabled.dat"
UVM_INFO @ 10.380001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| chip_sw_keymgr_dpe_key_derivation_jitter_en | 61098526086328931817402081638143894789442380443946599226471393414548535023891 | 284 |
UVM_FATAL @ 10.380001 us: (dv_utils_pkg.sv:266) [dv_utils_pkg::sw_symbol_get_addr_size.unmblk2] Check failed (ret) Failed to read line from "kJitterEnabled.dat"
UVM_INFO @ 10.380001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| chip_sw_kmac_mode_kmac_jitter_en | 13429153043584297486111567082851674833019351218544472678275312367342000223308 | 284 |
UVM_FATAL @ 10.100001 us: (dv_utils_pkg.sv:266) [dv_utils_pkg::sw_symbol_get_addr_size.unmblk2] Check failed (ret) Failed to read line from "kJitterEnabled.dat"
UVM_INFO @ 10.100001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| chip_sw_otbn_ecdsa_op_irq_jitter_en_reduced_freq | 6306444231312864466865430669409401683578120198177040703977203133646928340216 | 284 |
UVM_FATAL @ 10.240001 us: (dv_utils_pkg.sv:266) [dv_utils_pkg::sw_symbol_get_addr_size.unmblk2] Check failed (ret) Failed to read line from "kJitterEnabled.dat"
UVM_INFO @ 10.240001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| chip_sw_aes_enc_jitter_en_reduced_freq | 55001554047087132551620890466338838214485206235349184108006050358177451236856 | 284 |
UVM_FATAL @ 10.400001 us: (dv_utils_pkg.sv:266) [dv_utils_pkg::sw_symbol_get_addr_size.unmblk2] Check failed (ret) Failed to read line from "kJitterEnabled.dat"
UVM_INFO @ 10.400001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| chip_sw_hmac_enc_jitter_en_reduced_freq | 78316100737645383608565815950008427776483171635463963598673429207158717735044 | 284 |
UVM_FATAL @ 10.380001 us: (dv_utils_pkg.sv:266) [dv_utils_pkg::sw_symbol_get_addr_size.unmblk2] Check failed (ret) Failed to read line from "kJitterEnabled.dat"
UVM_INFO @ 10.380001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| chip_sw_keymgr_dpe_key_derivation_jitter_en_reduced_freq | 26489722283941667318111799336898230035451775342325931999794755876199190583172 | 284 |
UVM_FATAL @ 10.340001 us: (dv_utils_pkg.sv:266) [dv_utils_pkg::sw_symbol_get_addr_size.unmblk2] Check failed (ret) Failed to read line from "kJitterEnabled.dat"
UVM_INFO @ 10.340001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| chip_sw_kmac_mode_kmac_jitter_en_reduced_freq | 7861202961533060425053753944754720280125821742395893687260944877787471459459 | 284 |
UVM_FATAL @ 10.400001 us: (dv_utils_pkg.sv:266) [dv_utils_pkg::sw_symbol_get_addr_size.unmblk2] Check failed (ret) Failed to read line from "kJitterEnabled.dat"
UVM_INFO @ 10.400001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| chip_sw_sram_ctrl_scrambled_access_jitter_en_reduced_freq | 5576152014113381133031954939675636177999963712822500157049536761132972655791 | 284 |
UVM_FATAL @ 10.180001 us: (dv_utils_pkg.sv:266) [dv_utils_pkg::sw_symbol_get_addr_size.unmblk2] Check failed (ret) Failed to read line from "kJitterEnabled.dat"
UVM_INFO @ 10.180001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| chip_sw_csrng_edn_concurrency_reduced_freq | 58017011679682441014162186630355030055973493279183125490387693197449253628755 | 284 |
UVM_FATAL @ 10.100001 us: (dv_utils_pkg.sv:266) [dv_utils_pkg::sw_symbol_get_addr_size.unmblk2] Check failed (ret) Failed to read line from "kJitterEnabled.dat"
UVM_INFO @ 10.100001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| UVM_ERROR @ * us: (sw_logger_if.sv:526) [rv_core_ibex_nmi_irq_test_sim_dv(sw/device/tests/rv_core_ibex_nmi_irq_test.c:172)] CHECK-fail: Timed out after * usec (* CPU cycles) waiting for nmi_fired | ||||
| chip_sw_rv_core_ibex_nmi_irq | 104983053045308345754325806151373222593880793029511476922491425688640939837771 | 294 |
UVM_ERROR @ 271.153500 us: (sw_logger_if.sv:526) [rv_core_ibex_nmi_irq_test_sim_dv(sw/device/tests/rv_core_ibex_nmi_irq_test.c:172)] CHECK-fail: Timed out after 1000 usec (100000 CPU cycles) waiting for nmi_fired
UVM_INFO @ 271.153500 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| UVM_ERROR @ * us: (chip_sw_keymgr_dpe_key_derivation_vseq.sv:92) [chip_sw_keymgr_dpe_key_derivation_vseq] Check failed stage_*_key == get_otp_root_key() (* [*] vs * [*]) Expecting boot stage * key to equal creator root key (UDS) from OTP | ||||
| chip_sw_keymgr_dpe_key_derivation | 56101211362846525211787918508980219678019460154233603180125390030809789744121 | 312 |
UVM_ERROR @ 305.032500 us: (chip_sw_keymgr_dpe_key_derivation_vseq.sv:92) [uvm_test_top.env.virtual_sequencer.chip_sw_keymgr_dpe_key_derivation_vseq] Check failed stage_0_key == get_otp_root_key() (11110157094722515261074688167668681538830912973383447841843804434990479395042102737762181223779369207795490888439527388879104006038994549404953283796491356 [0xd4215110aae844f2f7a7603fbfb6f3545b073c9def6c4889d8d3681ee5e09dd35277e1e17f1076d6800bd13c9a690428f1ac7bcc8c3d21c37136056170055c5c] vs 11215554652525030750439897942755197157874305238639658102584100640388816185692128121488765684043362451728722615066578775045707746854198728065777318205152348 [0xd6247d3baae844f2f7a7603fbfb6f3545b073c9def6c4889d8d3681ee5e09dd35072cdca7f1076d6800bd13c9a690428f1ac7bcc8c3d21c37136056170055c5c]) Expecting boot stage 0 key to equal creator root key (UDS) from OTP
UVM_INFO @ 305.032500 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| chip_sw_keymgr_dpe_key_derivation_prod | 38883291902577500724150986987134556866735993791317828835857638429229469161762 | 312 |
UVM_ERROR @ 305.219500 us: (chip_sw_keymgr_dpe_key_derivation_vseq.sv:92) [uvm_test_top.env.virtual_sequencer.chip_sw_keymgr_dpe_key_derivation_vseq] Check failed stage_0_key == get_otp_root_key() (9358105983088111384440457735650812564683680192723127777654439020068306114983132065943769703021003756014927280815243385364535756707430236549500669947894876 [0xb2ad781eaae844f2f7a7603fbfb6f3545b073c9def6c4889d8d3681ee5e09dd334fbc8ef7f1076d6800bd13c9a690428f1ac7bcc8c3d21c37136056170055c5c] vs 11215554652525030750439897942755197157874305238639658102584100640388816185692128121488765684043362451728722615066578775045707746854198728065777318205152348 [0xd6247d3baae844f2f7a7603fbfb6f3545b073c9def6c4889d8d3681ee5e09dd35072cdca7f1076d6800bd13c9a690428f1ac7bcc8c3d21c37136056170055c5c]) Expecting boot stage 0 key to equal creator root key (UDS) from OTP
UVM_INFO @ 305.219500 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| UVM_ERROR @ * us: (cip_base_scoreboard.sv:582) scoreboard [scoreboard] On interface chip_reg_block, item had unexpected d_error value(predicted *, but saw *). | ||||
| chip_jtag_csr_rw | 87508459741897746474910932897559274772032937963656712182587910063416445160767 | 5922 |
UVM_ERROR @ 117.027500 us: (cip_base_scoreboard.sv:582) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] On interface chip_reg_block, item had unexpected d_error value(predicted 1, but saw 0).
TL item was: req: (cip_tl_seq_item@180660) { a_addr: 'h30480000 a_data: 'hc5d8d7b4 a_mask: 'hf a_size: 'h2 a_param: 'h0 a_source: 'h0 a_opcode: 'h1 a_user: 'h248eb d_param: 'h0 d_source: 'h0 d_data: 'h0 d_size: 'h2 d_opcode: 'h0 d_error: 'h0 d_sink: 'h0 d_user: 'h1caa a_valid_delay: 'h0 d_valid_delay: 'h0 a_valid_len: 'h0 d_valid_len: 'h0 req_abort_after_a_valid_len: 'h0 rsp_abort_after_d_valid_len: 'h0 req_completed: 'h0 rsp_completed: 'h0 tl_intg_err_type: TlIntgErrNone max_ecc_errors: 'h3 }
Reasons for predicted error: '{"Unmapped address"}.
UVM_INFO @ 117.027500 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| chip_jtag_mem_access | 48984868777014890008636140963318488036046700051850729563000389818875693927986 | 5922 |
UVM_ERROR @ 117.030500 us: (cip_base_scoreboard.sv:582) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] On interface chip_reg_block, item had unexpected d_error value(predicted 1, but saw 0).
TL item was: req: (cip_tl_seq_item@180659) { a_addr: 'h30480000 a_data: 'hc8fe9da4 a_mask: 'hf a_size: 'h2 a_param: 'h0 a_source: 'h1b a_opcode: 'h1 a_user: 'h248e1 d_param: 'h0 d_source: 'h1b d_data: 'h0 d_size: 'h2 d_opcode: 'h0 d_error: 'h0 d_sink: 'h0 d_user: 'h1caa a_valid_delay: 'h0 d_valid_delay: 'h0 a_valid_len: 'h0 d_valid_len: 'h0 req_abort_after_a_valid_len: 'h0 rsp_abort_after_d_valid_len: 'h0 req_completed: 'h0 rsp_completed: 'h0 tl_intg_err_type: TlIntgErrNone max_ecc_errors: 'h3 }
Reasons for predicted error: '{"Unmapped address"}.
UVM_INFO @ 117.030500 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| UVM_ERROR @ * us: (sw_logger_if.sv:526) [dma_abort_sim_dv(sw/device/tests/dma_abort.c:77)] CHECK-fail: Timed out after * usec (* CPU cycles) waiting for kSoftwareBarrier == * | ||||
| chip_sw_dma_abort | 48646647797801231564318253398303952030839381671979195520003174363459608470547 | 297 |
UVM_ERROR @ 212.103500 us: (sw_logger_if.sv:526) [dma_abort_sim_dv(sw/device/tests/dma_abort.c:77)] CHECK-fail: Timed out after 500 usec (50000 CPU cycles) waiting for kSoftwareBarrier == 1
UVM_INFO @ 212.103500 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| xmsim: *E,CGNCTN: Coverage dumping for covergroup instance variable max_delay_cg (/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_xbar_env_*/xbar_env_cov.sv:25) with 'dma__host' as instance name failed, as another covergroup instance variable bit_toggle_cg (/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_dv_lib_*/bit_toggle_cg_wrap.sv:30) with the same instance name 'dma__host' in the same scope was earlier saved to the database. | ||||
| xbar_smoke | 86494230295419625313477589125108376402123753739578082644820336643743677396031 | 314 |
xmsim: *E,CGNCTN: Coverage dumping for covergroup instance variable max_delay_cg (/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_xbar_env_0.1/xbar_env_cov.sv:25) with 'dma__host' as instance name failed, as another covergroup instance variable bit_toggle_cg (/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_dv_lib_0/bit_toggle_cg_wrap.sv:30) with the same instance name 'dma__host' in the same scope was earlier saved to the database.
xmsim: *E,CGNCTN: Coverage dumping for covergroup instance variable max_delay_cg (/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_xbar_env_0.1/xbar_env_cov.sv:25) with 'mbx0__sram' as instance name failed, as another covergroup instance variable bit_toggle_cg (/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_dv_lib_0/bit_toggle_cg_wrap.sv:30) with the same instance name 'mbx0__sram' in the same scope was earlier saved to the database.
xmsim: *E,CGNCTN: Coverage dumping for covergroup instance variable max_delay_cg (/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_xbar_env_0.1/xbar_env_cov.sv:25) with 'mbx1__sram' as instance name failed, as another covergroup instance variable bit_toggle_cg (/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_dv_lib_0/bit_toggle_cg_wrap.sv:30) with the same instance name 'mbx1__sram' in the same scope was earlier saved to the database.
xmsim: *E,CGNCTN: Coverage dumping for covergroup instance variable max_delay_cg (/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_xbar_env_0.1/xbar_env_cov.sv:25) with 'mbx2__sram' as instance name failed, as another covergroup instance variable bit_toggle_cg (/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_dv_lib_0/bit_toggle_cg_wrap.sv:30) with the same instance name 'mbx2__sram' in the same scope was earlier saved to the database.
xmsim: *E,CGNCTN: Coverage dumping for covergroup instance variable max_delay_cg (/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_xbar_env_0.1/xbar_env_cov.sv:25) with 'mbx3__sram' as instance name failed, as another covergroup instance variable bit_toggle_cg (/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_dv_lib_0/bit_toggle_cg_wrap.sv:30) with the same instance name 'mbx3__sram' in the same scope was earlier saved to the database.
|
|
| xbar_smoke_zero_delays | 22224075757881481745685852648316741341078304781862590515555740731718575803619 | 314 |
xmsim: *E,CGNCTN: Coverage dumping for covergroup instance variable max_delay_cg (/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_xbar_env_0.1/xbar_env_cov.sv:25) with 'dma__host' as instance name failed, as another covergroup instance variable bit_toggle_cg (/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_dv_lib_0/bit_toggle_cg_wrap.sv:30) with the same instance name 'dma__host' in the same scope was earlier saved to the database.
xmsim: *E,CGNCTN: Coverage dumping for covergroup instance variable max_delay_cg (/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_xbar_env_0.1/xbar_env_cov.sv:25) with 'mbx0__sram' as instance name failed, as another covergroup instance variable bit_toggle_cg (/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_dv_lib_0/bit_toggle_cg_wrap.sv:30) with the same instance name 'mbx0__sram' in the same scope was earlier saved to the database.
xmsim: *E,CGNCTN: Coverage dumping for covergroup instance variable max_delay_cg (/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_xbar_env_0.1/xbar_env_cov.sv:25) with 'mbx1__sram' as instance name failed, as another covergroup instance variable bit_toggle_cg (/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_dv_lib_0/bit_toggle_cg_wrap.sv:30) with the same instance name 'mbx1__sram' in the same scope was earlier saved to the database.
xmsim: *E,CGNCTN: Coverage dumping for covergroup instance variable max_delay_cg (/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_xbar_env_0.1/xbar_env_cov.sv:25) with 'mbx2__sram' as instance name failed, as another covergroup instance variable bit_toggle_cg (/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_dv_lib_0/bit_toggle_cg_wrap.sv:30) with the same instance name 'mbx2__sram' in the same scope was earlier saved to the database.
xmsim: *E,CGNCTN: Coverage dumping for covergroup instance variable max_delay_cg (/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_xbar_env_0.1/xbar_env_cov.sv:25) with 'mbx3__sram' as instance name failed, as another covergroup instance variable bit_toggle_cg (/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_dv_lib_0/bit_toggle_cg_wrap.sv:30) with the same instance name 'mbx3__sram' in the same scope was earlier saved to the database.
|
|
| xbar_smoke_large_delays | 80116500558390907365493455709669171386158583779578022035321884551747506471853 | 314 |
xmsim: *E,CGNCTN: Coverage dumping for covergroup instance variable max_delay_cg (/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_xbar_env_0.1/xbar_env_cov.sv:25) with 'dma__host' as instance name failed, as another covergroup instance variable bit_toggle_cg (/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_dv_lib_0/bit_toggle_cg_wrap.sv:30) with the same instance name 'dma__host' in the same scope was earlier saved to the database.
xmsim: *E,CGNCTN: Coverage dumping for covergroup instance variable max_delay_cg (/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_xbar_env_0.1/xbar_env_cov.sv:25) with 'mbx0__sram' as instance name failed, as another covergroup instance variable bit_toggle_cg (/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_dv_lib_0/bit_toggle_cg_wrap.sv:30) with the same instance name 'mbx0__sram' in the same scope was earlier saved to the database.
xmsim: *E,CGNCTN: Coverage dumping for covergroup instance variable max_delay_cg (/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_xbar_env_0.1/xbar_env_cov.sv:25) with 'mbx1__sram' as instance name failed, as another covergroup instance variable bit_toggle_cg (/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_dv_lib_0/bit_toggle_cg_wrap.sv:30) with the same instance name 'mbx1__sram' in the same scope was earlier saved to the database.
xmsim: *E,CGNCTN: Coverage dumping for covergroup instance variable max_delay_cg (/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_xbar_env_0.1/xbar_env_cov.sv:25) with 'mbx2__sram' as instance name failed, as another covergroup instance variable bit_toggle_cg (/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_dv_lib_0/bit_toggle_cg_wrap.sv:30) with the same instance name 'mbx2__sram' in the same scope was earlier saved to the database.
xmsim: *E,CGNCTN: Coverage dumping for covergroup instance variable max_delay_cg (/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_xbar_env_0.1/xbar_env_cov.sv:25) with 'mbx3__sram' as instance name failed, as another covergroup instance variable bit_toggle_cg (/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_dv_lib_0/bit_toggle_cg_wrap.sv:30) with the same instance name 'mbx3__sram' in the same scope was earlier saved to the database.
|
|
| xbar_smoke_slow_rsp | 16629876602995690807408153044344706123954288122164341642408860526053580580713 | 314 |
xmsim: *E,CGNCTN: Coverage dumping for covergroup instance variable max_delay_cg (/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_xbar_env_0.1/xbar_env_cov.sv:25) with 'dma__host' as instance name failed, as another covergroup instance variable bit_toggle_cg (/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_dv_lib_0/bit_toggle_cg_wrap.sv:30) with the same instance name 'dma__host' in the same scope was earlier saved to the database.
xmsim: *E,CGNCTN: Coverage dumping for covergroup instance variable max_delay_cg (/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_xbar_env_0.1/xbar_env_cov.sv:25) with 'mbx0__sram' as instance name failed, as another covergroup instance variable bit_toggle_cg (/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_dv_lib_0/bit_toggle_cg_wrap.sv:30) with the same instance name 'mbx0__sram' in the same scope was earlier saved to the database.
xmsim: *E,CGNCTN: Coverage dumping for covergroup instance variable max_delay_cg (/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_xbar_env_0.1/xbar_env_cov.sv:25) with 'mbx1__sram' as instance name failed, as another covergroup instance variable bit_toggle_cg (/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_dv_lib_0/bit_toggle_cg_wrap.sv:30) with the same instance name 'mbx1__sram' in the same scope was earlier saved to the database.
xmsim: *E,CGNCTN: Coverage dumping for covergroup instance variable max_delay_cg (/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_xbar_env_0.1/xbar_env_cov.sv:25) with 'mbx2__sram' as instance name failed, as another covergroup instance variable bit_toggle_cg (/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_dv_lib_0/bit_toggle_cg_wrap.sv:30) with the same instance name 'mbx2__sram' in the same scope was earlier saved to the database.
xmsim: *E,CGNCTN: Coverage dumping for covergroup instance variable max_delay_cg (/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_xbar_env_0.1/xbar_env_cov.sv:25) with 'mbx3__sram' as instance name failed, as another covergroup instance variable bit_toggle_cg (/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_dv_lib_0/bit_toggle_cg_wrap.sv:30) with the same instance name 'mbx3__sram' in the same scope was earlier saved to the database.
|
|
| xbar_random | 42163170598108858531977061881306807470371990491155273770227800693751743132800 | 345 |
xmsim: *E,CGNCTN: Coverage dumping for covergroup instance variable max_delay_cg (/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_xbar_env_0.1/xbar_env_cov.sv:25) with 'dma__host' as instance name failed, as another covergroup instance variable bit_toggle_cg (/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_dv_lib_0/bit_toggle_cg_wrap.sv:30) with the same instance name 'dma__host' in the same scope was earlier saved to the database.
xmsim: *E,CGNCTN: Coverage dumping for covergroup instance variable max_delay_cg (/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_xbar_env_0.1/xbar_env_cov.sv:25) with 'mbx0__sram' as instance name failed, as another covergroup instance variable bit_toggle_cg (/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_dv_lib_0/bit_toggle_cg_wrap.sv:30) with the same instance name 'mbx0__sram' in the same scope was earlier saved to the database.
xmsim: *E,CGNCTN: Coverage dumping for covergroup instance variable max_delay_cg (/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_xbar_env_0.1/xbar_env_cov.sv:25) with 'mbx1__sram' as instance name failed, as another covergroup instance variable bit_toggle_cg (/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_dv_lib_0/bit_toggle_cg_wrap.sv:30) with the same instance name 'mbx1__sram' in the same scope was earlier saved to the database.
xmsim: *E,CGNCTN: Coverage dumping for covergroup instance variable max_delay_cg (/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_xbar_env_0.1/xbar_env_cov.sv:25) with 'mbx2__sram' as instance name failed, as another covergroup instance variable bit_toggle_cg (/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_dv_lib_0/bit_toggle_cg_wrap.sv:30) with the same instance name 'mbx2__sram' in the same scope was earlier saved to the database.
xmsim: *E,CGNCTN: Coverage dumping for covergroup instance variable max_delay_cg (/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_xbar_env_0.1/xbar_env_cov.sv:25) with 'mbx3__sram' as instance name failed, as another covergroup instance variable bit_toggle_cg (/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_dv_lib_0/bit_toggle_cg_wrap.sv:30) with the same instance name 'mbx3__sram' in the same scope was earlier saved to the database.
|
|
| xbar_random_zero_delays | 99025319152847224608301645854998621190387851283274608139623727959786705314644 | 480 |
xmsim: *E,CGNCTN: Coverage dumping for covergroup instance variable max_delay_cg (/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_xbar_env_0.1/xbar_env_cov.sv:25) with 'dma__host' as instance name failed, as another covergroup instance variable bit_toggle_cg (/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_dv_lib_0/bit_toggle_cg_wrap.sv:30) with the same instance name 'dma__host' in the same scope was earlier saved to the database.
xmsim: *E,CGNCTN: Coverage dumping for covergroup instance variable max_delay_cg (/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_xbar_env_0.1/xbar_env_cov.sv:25) with 'mbx0__sram' as instance name failed, as another covergroup instance variable bit_toggle_cg (/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_dv_lib_0/bit_toggle_cg_wrap.sv:30) with the same instance name 'mbx0__sram' in the same scope was earlier saved to the database.
xmsim: *E,CGNCTN: Coverage dumping for covergroup instance variable max_delay_cg (/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_xbar_env_0.1/xbar_env_cov.sv:25) with 'mbx1__sram' as instance name failed, as another covergroup instance variable bit_toggle_cg (/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_dv_lib_0/bit_toggle_cg_wrap.sv:30) with the same instance name 'mbx1__sram' in the same scope was earlier saved to the database.
xmsim: *E,CGNCTN: Coverage dumping for covergroup instance variable max_delay_cg (/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_xbar_env_0.1/xbar_env_cov.sv:25) with 'mbx2__sram' as instance name failed, as another covergroup instance variable bit_toggle_cg (/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_dv_lib_0/bit_toggle_cg_wrap.sv:30) with the same instance name 'mbx2__sram' in the same scope was earlier saved to the database.
xmsim: *E,CGNCTN: Coverage dumping for covergroup instance variable max_delay_cg (/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_xbar_env_0.1/xbar_env_cov.sv:25) with 'mbx3__sram' as instance name failed, as another covergroup instance variable bit_toggle_cg (/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_dv_lib_0/bit_toggle_cg_wrap.sv:30) with the same instance name 'mbx3__sram' in the same scope was earlier saved to the database.
|
|
| xbar_random_large_delays | 70864131020603773702690729049465671642067021166066959182825319963647993177098 | 360 |
xmsim: *E,CGNCTN: Coverage dumping for covergroup instance variable max_delay_cg (/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_xbar_env_0.1/xbar_env_cov.sv:25) with 'dma__host' as instance name failed, as another covergroup instance variable bit_toggle_cg (/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_dv_lib_0/bit_toggle_cg_wrap.sv:30) with the same instance name 'dma__host' in the same scope was earlier saved to the database.
xmsim: *E,CGNCTN: Coverage dumping for covergroup instance variable max_delay_cg (/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_xbar_env_0.1/xbar_env_cov.sv:25) with 'mbx0__sram' as instance name failed, as another covergroup instance variable bit_toggle_cg (/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_dv_lib_0/bit_toggle_cg_wrap.sv:30) with the same instance name 'mbx0__sram' in the same scope was earlier saved to the database.
xmsim: *E,CGNCTN: Coverage dumping for covergroup instance variable max_delay_cg (/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_xbar_env_0.1/xbar_env_cov.sv:25) with 'mbx1__sram' as instance name failed, as another covergroup instance variable bit_toggle_cg (/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_dv_lib_0/bit_toggle_cg_wrap.sv:30) with the same instance name 'mbx1__sram' in the same scope was earlier saved to the database.
xmsim: *E,CGNCTN: Coverage dumping for covergroup instance variable max_delay_cg (/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_xbar_env_0.1/xbar_env_cov.sv:25) with 'mbx2__sram' as instance name failed, as another covergroup instance variable bit_toggle_cg (/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_dv_lib_0/bit_toggle_cg_wrap.sv:30) with the same instance name 'mbx2__sram' in the same scope was earlier saved to the database.
xmsim: *E,CGNCTN: Coverage dumping for covergroup instance variable max_delay_cg (/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_xbar_env_0.1/xbar_env_cov.sv:25) with 'mbx3__sram' as instance name failed, as another covergroup instance variable bit_toggle_cg (/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_dv_lib_0/bit_toggle_cg_wrap.sv:30) with the same instance name 'mbx3__sram' in the same scope was earlier saved to the database.
|
|
| xbar_random_slow_rsp | 87185017639325451254868800467507359477982549137596140942209579062517715833860 | 375 |
xmsim: *E,CGNCTN: Coverage dumping for covergroup instance variable max_delay_cg (/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_xbar_env_0.1/xbar_env_cov.sv:25) with 'dma__host' as instance name failed, as another covergroup instance variable bit_toggle_cg (/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_dv_lib_0/bit_toggle_cg_wrap.sv:30) with the same instance name 'dma__host' in the same scope was earlier saved to the database.
xmsim: *E,CGNCTN: Coverage dumping for covergroup instance variable max_delay_cg (/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_xbar_env_0.1/xbar_env_cov.sv:25) with 'mbx0__sram' as instance name failed, as another covergroup instance variable bit_toggle_cg (/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_dv_lib_0/bit_toggle_cg_wrap.sv:30) with the same instance name 'mbx0__sram' in the same scope was earlier saved to the database.
xmsim: *E,CGNCTN: Coverage dumping for covergroup instance variable max_delay_cg (/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_xbar_env_0.1/xbar_env_cov.sv:25) with 'mbx1__sram' as instance name failed, as another covergroup instance variable bit_toggle_cg (/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_dv_lib_0/bit_toggle_cg_wrap.sv:30) with the same instance name 'mbx1__sram' in the same scope was earlier saved to the database.
xmsim: *E,CGNCTN: Coverage dumping for covergroup instance variable max_delay_cg (/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_xbar_env_0.1/xbar_env_cov.sv:25) with 'mbx2__sram' as instance name failed, as another covergroup instance variable bit_toggle_cg (/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_dv_lib_0/bit_toggle_cg_wrap.sv:30) with the same instance name 'mbx2__sram' in the same scope was earlier saved to the database.
xmsim: *E,CGNCTN: Coverage dumping for covergroup instance variable max_delay_cg (/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_xbar_env_0.1/xbar_env_cov.sv:25) with 'mbx3__sram' as instance name failed, as another covergroup instance variable bit_toggle_cg (/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_dv_lib_0/bit_toggle_cg_wrap.sv:30) with the same instance name 'mbx3__sram' in the same scope was earlier saved to the database.
|
|
| xbar_access_same_device | 79196124058529330299142466973024061295137263836475022197822603364212632150806 | 345 |
xmsim: *E,CGNCTN: Coverage dumping for covergroup instance variable max_delay_cg (/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_xbar_env_0.1/xbar_env_cov.sv:25) with 'dma__host' as instance name failed, as another covergroup instance variable bit_toggle_cg (/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_dv_lib_0/bit_toggle_cg_wrap.sv:30) with the same instance name 'dma__host' in the same scope was earlier saved to the database.
xmsim: *E,CGNCTN: Coverage dumping for covergroup instance variable max_delay_cg (/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_xbar_env_0.1/xbar_env_cov.sv:25) with 'mbx0__sram' as instance name failed, as another covergroup instance variable bit_toggle_cg (/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_dv_lib_0/bit_toggle_cg_wrap.sv:30) with the same instance name 'mbx0__sram' in the same scope was earlier saved to the database.
xmsim: *E,CGNCTN: Coverage dumping for covergroup instance variable max_delay_cg (/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_xbar_env_0.1/xbar_env_cov.sv:25) with 'mbx1__sram' as instance name failed, as another covergroup instance variable bit_toggle_cg (/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_dv_lib_0/bit_toggle_cg_wrap.sv:30) with the same instance name 'mbx1__sram' in the same scope was earlier saved to the database.
xmsim: *E,CGNCTN: Coverage dumping for covergroup instance variable max_delay_cg (/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_xbar_env_0.1/xbar_env_cov.sv:25) with 'mbx2__sram' as instance name failed, as another covergroup instance variable bit_toggle_cg (/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_dv_lib_0/bit_toggle_cg_wrap.sv:30) with the same instance name 'mbx2__sram' in the same scope was earlier saved to the database.
xmsim: *E,CGNCTN: Coverage dumping for covergroup instance variable max_delay_cg (/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_xbar_env_0.1/xbar_env_cov.sv:25) with 'mbx3__sram' as instance name failed, as another covergroup instance variable bit_toggle_cg (/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_dv_lib_0/bit_toggle_cg_wrap.sv:30) with the same instance name 'mbx3__sram' in the same scope was earlier saved to the database.
|
|
| xbar_access_same_device_slow_rsp | 113907065142509461897656223244450039943334933124280048529917229366499396010899 | 435 |
xmsim: *E,CGNCTN: Coverage dumping for covergroup instance variable max_delay_cg (/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_xbar_env_0.1/xbar_env_cov.sv:25) with 'dma__host' as instance name failed, as another covergroup instance variable bit_toggle_cg (/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_dv_lib_0/bit_toggle_cg_wrap.sv:30) with the same instance name 'dma__host' in the same scope was earlier saved to the database.
xmsim: *E,CGNCTN: Coverage dumping for covergroup instance variable max_delay_cg (/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_xbar_env_0.1/xbar_env_cov.sv:25) with 'mbx0__sram' as instance name failed, as another covergroup instance variable bit_toggle_cg (/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_dv_lib_0/bit_toggle_cg_wrap.sv:30) with the same instance name 'mbx0__sram' in the same scope was earlier saved to the database.
xmsim: *E,CGNCTN: Coverage dumping for covergroup instance variable max_delay_cg (/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_xbar_env_0.1/xbar_env_cov.sv:25) with 'mbx1__sram' as instance name failed, as another covergroup instance variable bit_toggle_cg (/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_dv_lib_0/bit_toggle_cg_wrap.sv:30) with the same instance name 'mbx1__sram' in the same scope was earlier saved to the database.
xmsim: *E,CGNCTN: Coverage dumping for covergroup instance variable max_delay_cg (/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_xbar_env_0.1/xbar_env_cov.sv:25) with 'mbx2__sram' as instance name failed, as another covergroup instance variable bit_toggle_cg (/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_dv_lib_0/bit_toggle_cg_wrap.sv:30) with the same instance name 'mbx2__sram' in the same scope was earlier saved to the database.
xmsim: *E,CGNCTN: Coverage dumping for covergroup instance variable max_delay_cg (/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_xbar_env_0.1/xbar_env_cov.sv:25) with 'mbx3__sram' as instance name failed, as another covergroup instance variable bit_toggle_cg (/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_dv_lib_0/bit_toggle_cg_wrap.sv:30) with the same instance name 'mbx3__sram' in the same scope was earlier saved to the database.
|
|
| xbar_same_source | 106701084149136433005683476195447566636740380465467239522898193598639976061471 | 1290 |
xmsim: *E,CGNCTN: Coverage dumping for covergroup instance variable max_delay_cg (/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_xbar_env_0.1/xbar_env_cov.sv:25) with 'dma__host' as instance name failed, as another covergroup instance variable bit_toggle_cg (/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_dv_lib_0/bit_toggle_cg_wrap.sv:30) with the same instance name 'dma__host' in the same scope was earlier saved to the database.
xmsim: *E,CGNCTN: Coverage dumping for covergroup instance variable max_delay_cg (/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_xbar_env_0.1/xbar_env_cov.sv:25) with 'mbx0__sram' as instance name failed, as another covergroup instance variable bit_toggle_cg (/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_dv_lib_0/bit_toggle_cg_wrap.sv:30) with the same instance name 'mbx0__sram' in the same scope was earlier saved to the database.
xmsim: *E,CGNCTN: Coverage dumping for covergroup instance variable max_delay_cg (/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_xbar_env_0.1/xbar_env_cov.sv:25) with 'mbx1__sram' as instance name failed, as another covergroup instance variable bit_toggle_cg (/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_dv_lib_0/bit_toggle_cg_wrap.sv:30) with the same instance name 'mbx1__sram' in the same scope was earlier saved to the database.
xmsim: *E,CGNCTN: Coverage dumping for covergroup instance variable max_delay_cg (/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_xbar_env_0.1/xbar_env_cov.sv:25) with 'mbx2__sram' as instance name failed, as another covergroup instance variable bit_toggle_cg (/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_dv_lib_0/bit_toggle_cg_wrap.sv:30) with the same instance name 'mbx2__sram' in the same scope was earlier saved to the database.
xmsim: *E,CGNCTN: Coverage dumping for covergroup instance variable max_delay_cg (/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_xbar_env_0.1/xbar_env_cov.sv:25) with 'mbx3__sram' as instance name failed, as another covergroup instance variable bit_toggle_cg (/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_dv_lib_0/bit_toggle_cg_wrap.sv:30) with the same instance name 'mbx3__sram' in the same scope was earlier saved to the database.
|
|
| xbar_error_random | 90665101108324355242221084334618930803616744948457445359414528340614197114278 | 375 |
xmsim: *E,CGNCTN: Coverage dumping for covergroup instance variable max_delay_cg (/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_xbar_env_0.1/xbar_env_cov.sv:25) with 'dma__host' as instance name failed, as another covergroup instance variable bit_toggle_cg (/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_dv_lib_0/bit_toggle_cg_wrap.sv:30) with the same instance name 'dma__host' in the same scope was earlier saved to the database.
xmsim: *E,CGNCTN: Coverage dumping for covergroup instance variable max_delay_cg (/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_xbar_env_0.1/xbar_env_cov.sv:25) with 'mbx0__sram' as instance name failed, as another covergroup instance variable bit_toggle_cg (/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_dv_lib_0/bit_toggle_cg_wrap.sv:30) with the same instance name 'mbx0__sram' in the same scope was earlier saved to the database.
xmsim: *E,CGNCTN: Coverage dumping for covergroup instance variable max_delay_cg (/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_xbar_env_0.1/xbar_env_cov.sv:25) with 'mbx1__sram' as instance name failed, as another covergroup instance variable bit_toggle_cg (/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_dv_lib_0/bit_toggle_cg_wrap.sv:30) with the same instance name 'mbx1__sram' in the same scope was earlier saved to the database.
xmsim: *E,CGNCTN: Coverage dumping for covergroup instance variable max_delay_cg (/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_xbar_env_0.1/xbar_env_cov.sv:25) with 'mbx2__sram' as instance name failed, as another covergroup instance variable bit_toggle_cg (/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_dv_lib_0/bit_toggle_cg_wrap.sv:30) with the same instance name 'mbx2__sram' in the same scope was earlier saved to the database.
xmsim: *E,CGNCTN: Coverage dumping for covergroup instance variable max_delay_cg (/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_xbar_env_0.1/xbar_env_cov.sv:25) with 'mbx3__sram' as instance name failed, as another covergroup instance variable bit_toggle_cg (/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_dv_lib_0/bit_toggle_cg_wrap.sv:30) with the same instance name 'mbx3__sram' in the same scope was earlier saved to the database.
|
|
| xbar_unmapped_addr | 105444971636666314644194089602493926162725887575409527854904395177321834963120 | 435 |
xmsim: *E,CGNCTN: Coverage dumping for covergroup instance variable max_delay_cg (/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_xbar_env_0.1/xbar_env_cov.sv:25) with 'dma__host' as instance name failed, as another covergroup instance variable bit_toggle_cg (/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_dv_lib_0/bit_toggle_cg_wrap.sv:30) with the same instance name 'dma__host' in the same scope was earlier saved to the database.
xmsim: *E,CGNCTN: Coverage dumping for covergroup instance variable max_delay_cg (/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_xbar_env_0.1/xbar_env_cov.sv:25) with 'mbx0__sram' as instance name failed, as another covergroup instance variable bit_toggle_cg (/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_dv_lib_0/bit_toggle_cg_wrap.sv:30) with the same instance name 'mbx0__sram' in the same scope was earlier saved to the database.
xmsim: *E,CGNCTN: Coverage dumping for covergroup instance variable max_delay_cg (/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_xbar_env_0.1/xbar_env_cov.sv:25) with 'mbx1__sram' as instance name failed, as another covergroup instance variable bit_toggle_cg (/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_dv_lib_0/bit_toggle_cg_wrap.sv:30) with the same instance name 'mbx1__sram' in the same scope was earlier saved to the database.
xmsim: *E,CGNCTN: Coverage dumping for covergroup instance variable max_delay_cg (/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_xbar_env_0.1/xbar_env_cov.sv:25) with 'mbx2__sram' as instance name failed, as another covergroup instance variable bit_toggle_cg (/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_dv_lib_0/bit_toggle_cg_wrap.sv:30) with the same instance name 'mbx2__sram' in the same scope was earlier saved to the database.
xmsim: *E,CGNCTN: Coverage dumping for covergroup instance variable max_delay_cg (/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_xbar_env_0.1/xbar_env_cov.sv:25) with 'mbx3__sram' as instance name failed, as another covergroup instance variable bit_toggle_cg (/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_dv_lib_0/bit_toggle_cg_wrap.sv:30) with the same instance name 'mbx3__sram' in the same scope was earlier saved to the database.
|
|
| xbar_error_and_unmapped_addr | 6509511627806012549274863655581645989520186066613057283711133114901965002369 | 570 |
xmsim: *E,CGNCTN: Coverage dumping for covergroup instance variable max_delay_cg (/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_xbar_env_0.1/xbar_env_cov.sv:25) with 'dma__host' as instance name failed, as another covergroup instance variable bit_toggle_cg (/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_dv_lib_0/bit_toggle_cg_wrap.sv:30) with the same instance name 'dma__host' in the same scope was earlier saved to the database.
xmsim: *E,CGNCTN: Coverage dumping for covergroup instance variable max_delay_cg (/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_xbar_env_0.1/xbar_env_cov.sv:25) with 'mbx0__sram' as instance name failed, as another covergroup instance variable bit_toggle_cg (/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_dv_lib_0/bit_toggle_cg_wrap.sv:30) with the same instance name 'mbx0__sram' in the same scope was earlier saved to the database.
xmsim: *E,CGNCTN: Coverage dumping for covergroup instance variable max_delay_cg (/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_xbar_env_0.1/xbar_env_cov.sv:25) with 'mbx1__sram' as instance name failed, as another covergroup instance variable bit_toggle_cg (/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_dv_lib_0/bit_toggle_cg_wrap.sv:30) with the same instance name 'mbx1__sram' in the same scope was earlier saved to the database.
xmsim: *E,CGNCTN: Coverage dumping for covergroup instance variable max_delay_cg (/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_xbar_env_0.1/xbar_env_cov.sv:25) with 'mbx2__sram' as instance name failed, as another covergroup instance variable bit_toggle_cg (/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_dv_lib_0/bit_toggle_cg_wrap.sv:30) with the same instance name 'mbx2__sram' in the same scope was earlier saved to the database.
xmsim: *E,CGNCTN: Coverage dumping for covergroup instance variable max_delay_cg (/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_xbar_env_0.1/xbar_env_cov.sv:25) with 'mbx3__sram' as instance name failed, as another covergroup instance variable bit_toggle_cg (/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_dv_lib_0/bit_toggle_cg_wrap.sv:30) with the same instance name 'mbx3__sram' in the same scope was earlier saved to the database.
|
|
| xbar_stress_all | 96756917239524069605632662483157141142270426437395343791454106968118049573140 | 843 |
xmsim: *E,CGNCTN: Coverage dumping for covergroup instance variable max_delay_cg (/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_xbar_env_0.1/xbar_env_cov.sv:25) with 'dma__host' as instance name failed, as another covergroup instance variable bit_toggle_cg (/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_dv_lib_0/bit_toggle_cg_wrap.sv:30) with the same instance name 'dma__host' in the same scope was earlier saved to the database.
xmsim: *E,CGNCTN: Coverage dumping for covergroup instance variable max_delay_cg (/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_xbar_env_0.1/xbar_env_cov.sv:25) with 'mbx0__sram' as instance name failed, as another covergroup instance variable bit_toggle_cg (/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_dv_lib_0/bit_toggle_cg_wrap.sv:30) with the same instance name 'mbx0__sram' in the same scope was earlier saved to the database.
xmsim: *E,CGNCTN: Coverage dumping for covergroup instance variable max_delay_cg (/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_xbar_env_0.1/xbar_env_cov.sv:25) with 'mbx1__sram' as instance name failed, as another covergroup instance variable bit_toggle_cg (/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_dv_lib_0/bit_toggle_cg_wrap.sv:30) with the same instance name 'mbx1__sram' in the same scope was earlier saved to the database.
xmsim: *E,CGNCTN: Coverage dumping for covergroup instance variable max_delay_cg (/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_xbar_env_0.1/xbar_env_cov.sv:25) with 'mbx2__sram' as instance name failed, as another covergroup instance variable bit_toggle_cg (/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_dv_lib_0/bit_toggle_cg_wrap.sv:30) with the same instance name 'mbx2__sram' in the same scope was earlier saved to the database.
xmsim: *E,CGNCTN: Coverage dumping for covergroup instance variable max_delay_cg (/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_xbar_env_0.1/xbar_env_cov.sv:25) with 'mbx3__sram' as instance name failed, as another covergroup instance variable bit_toggle_cg (/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_dv_lib_0/bit_toggle_cg_wrap.sv:30) with the same instance name 'mbx3__sram' in the same scope was earlier saved to the database.
|
|
| xbar_stress_all_with_rand_reset | 40954309995136528791934108052311935080684377969802091949401342050088063300807 | 25082 |
xmsim: *E,CGNCTN: Coverage dumping for covergroup instance variable max_delay_cg (/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_xbar_env_0.1/xbar_env_cov.sv:25) with 'dma__host' as instance name failed, as another covergroup instance variable bit_toggle_cg (/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_dv_lib_0/bit_toggle_cg_wrap.sv:30) with the same instance name 'dma__host' in the same scope was earlier saved to the database.
xmsim: *E,CGNCTN: Coverage dumping for covergroup instance variable max_delay_cg (/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_xbar_env_0.1/xbar_env_cov.sv:25) with 'mbx0__sram' as instance name failed, as another covergroup instance variable bit_toggle_cg (/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_dv_lib_0/bit_toggle_cg_wrap.sv:30) with the same instance name 'mbx0__sram' in the same scope was earlier saved to the database.
xmsim: *E,CGNCTN: Coverage dumping for covergroup instance variable max_delay_cg (/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_xbar_env_0.1/xbar_env_cov.sv:25) with 'mbx1__sram' as instance name failed, as another covergroup instance variable bit_toggle_cg (/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_dv_lib_0/bit_toggle_cg_wrap.sv:30) with the same instance name 'mbx1__sram' in the same scope was earlier saved to the database.
xmsim: *E,CGNCTN: Coverage dumping for covergroup instance variable max_delay_cg (/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_xbar_env_0.1/xbar_env_cov.sv:25) with 'mbx2__sram' as instance name failed, as another covergroup instance variable bit_toggle_cg (/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_dv_lib_0/bit_toggle_cg_wrap.sv:30) with the same instance name 'mbx2__sram' in the same scope was earlier saved to the database.
xmsim: *E,CGNCTN: Coverage dumping for covergroup instance variable max_delay_cg (/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_xbar_env_0.1/xbar_env_cov.sv:25) with 'mbx3__sram' as instance name failed, as another covergroup instance variable bit_toggle_cg (/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_dv_lib_0/bit_toggle_cg_wrap.sv:30) with the same instance name 'mbx3__sram' in the same scope was earlier saved to the database.
|
|
| xbar_stress_all_with_error | 33586890328280763497612057541625015146661696809427749190680135833921381571235 | 1175 |
xmsim: *E,CGNCTN: Coverage dumping for covergroup instance variable max_delay_cg (/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_xbar_env_0.1/xbar_env_cov.sv:25) with 'dma__host' as instance name failed, as another covergroup instance variable bit_toggle_cg (/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_dv_lib_0/bit_toggle_cg_wrap.sv:30) with the same instance name 'dma__host' in the same scope was earlier saved to the database.
xmsim: *E,CGNCTN: Coverage dumping for covergroup instance variable max_delay_cg (/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_xbar_env_0.1/xbar_env_cov.sv:25) with 'mbx0__sram' as instance name failed, as another covergroup instance variable bit_toggle_cg (/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_dv_lib_0/bit_toggle_cg_wrap.sv:30) with the same instance name 'mbx0__sram' in the same scope was earlier saved to the database.
xmsim: *E,CGNCTN: Coverage dumping for covergroup instance variable max_delay_cg (/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_xbar_env_0.1/xbar_env_cov.sv:25) with 'mbx1__sram' as instance name failed, as another covergroup instance variable bit_toggle_cg (/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_dv_lib_0/bit_toggle_cg_wrap.sv:30) with the same instance name 'mbx1__sram' in the same scope was earlier saved to the database.
xmsim: *E,CGNCTN: Coverage dumping for covergroup instance variable max_delay_cg (/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_xbar_env_0.1/xbar_env_cov.sv:25) with 'mbx2__sram' as instance name failed, as another covergroup instance variable bit_toggle_cg (/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_dv_lib_0/bit_toggle_cg_wrap.sv:30) with the same instance name 'mbx2__sram' in the same scope was earlier saved to the database.
xmsim: *E,CGNCTN: Coverage dumping for covergroup instance variable max_delay_cg (/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_xbar_env_0.1/xbar_env_cov.sv:25) with 'mbx3__sram' as instance name failed, as another covergroup instance variable bit_toggle_cg (/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_dv_lib_0/bit_toggle_cg_wrap.sv:30) with the same instance name 'mbx3__sram' in the same scope was earlier saved to the database.
|
|
| xbar_stress_all_with_reset_error | 41964188994956717121991785985551141579710737476870440292331110301372824086841 | 19705 |
xmsim: *E,CGNCTN: Coverage dumping for covergroup instance variable max_delay_cg (/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_xbar_env_0.1/xbar_env_cov.sv:25) with 'dma__host' as instance name failed, as another covergroup instance variable bit_toggle_cg (/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_dv_lib_0/bit_toggle_cg_wrap.sv:30) with the same instance name 'dma__host' in the same scope was earlier saved to the database.
xmsim: *E,CGNCTN: Coverage dumping for covergroup instance variable max_delay_cg (/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_xbar_env_0.1/xbar_env_cov.sv:25) with 'mbx0__sram' as instance name failed, as another covergroup instance variable bit_toggle_cg (/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_dv_lib_0/bit_toggle_cg_wrap.sv:30) with the same instance name 'mbx0__sram' in the same scope was earlier saved to the database.
xmsim: *E,CGNCTN: Coverage dumping for covergroup instance variable max_delay_cg (/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_xbar_env_0.1/xbar_env_cov.sv:25) with 'mbx1__sram' as instance name failed, as another covergroup instance variable bit_toggle_cg (/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_dv_lib_0/bit_toggle_cg_wrap.sv:30) with the same instance name 'mbx1__sram' in the same scope was earlier saved to the database.
xmsim: *E,CGNCTN: Coverage dumping for covergroup instance variable max_delay_cg (/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_xbar_env_0.1/xbar_env_cov.sv:25) with 'mbx2__sram' as instance name failed, as another covergroup instance variable bit_toggle_cg (/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_dv_lib_0/bit_toggle_cg_wrap.sv:30) with the same instance name 'mbx2__sram' in the same scope was earlier saved to the database.
xmsim: *E,CGNCTN: Coverage dumping for covergroup instance variable max_delay_cg (/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_xbar_env_0.1/xbar_env_cov.sv:25) with 'mbx3__sram' as instance name failed, as another covergroup instance variable bit_toggle_cg (/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_dv_lib_0/bit_toggle_cg_wrap.sv:30) with the same instance name 'mbx3__sram' in the same scope was earlier saved to the database.
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