| V1 |
|
0.00% |
| V2 |
|
0.00% |
| V2S |
|
0.00% |
| V3 |
|
0.00% |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| smoke | 0 | 1 | 0.00 | |||
| clkmgr_smoke | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| csr_hw_reset | 0 | 1 | 0.00 | |||
| clkmgr_csr_hw_reset | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| csr_rw | 0 | 1 | 0.00 | |||
| clkmgr_csr_rw | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| csr_bit_bash | 0 | 1 | 0.00 | |||
| clkmgr_csr_bit_bash | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| csr_aliasing | 0 | 1 | 0.00 | |||
| clkmgr_csr_aliasing | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| csr_mem_rw_with_rand_reset | 0 | 1 | 0.00 | |||
| clkmgr_csr_mem_rw_with_rand_reset | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| regwen_csr_and_corresponding_lockable_csr | 0 | 2 | 0.00 | |||
| clkmgr_csr_rw | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| clkmgr_csr_aliasing | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| peri_enables | 0 | 1 | 0.00 | |||
| clkmgr_peri | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| trans_enables | 0 | 1 | 0.00 | |||
| clkmgr_trans | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| clk_status | 0 | 1 | 0.00 | |||
| clkmgr_clk_status | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| jitter | 0 | 1 | 0.00 | |||
| clkmgr_smoke | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| frequency | 0 | 1 | 0.00 | |||
| clkmgr_frequency | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| frequency_timeout | 0 | 1 | 0.00 | |||
| clkmgr_frequency_timeout | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| frequency_overflow | 0 | 1 | 0.00 | |||
| clkmgr_frequency | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| stress_all | 0 | 1 | 0.00 | |||
| clkmgr_stress_all | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| alert_test | 0 | 1 | 0.00 | |||
| clkmgr_alert_test | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| tl_d_oob_addr_access | 0 | 1 | 0.00 | |||
| clkmgr_tl_errors | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| tl_d_illegal_access | 0 | 1 | 0.00 | |||
| clkmgr_tl_errors | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| tl_d_outstanding_access | 0 | 4 | 0.00 | |||
| clkmgr_csr_hw_reset | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| clkmgr_csr_rw | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| clkmgr_csr_aliasing | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| clkmgr_same_csr_outstanding | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| tl_d_partial_access | 0 | 4 | 0.00 | |||
| clkmgr_csr_hw_reset | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| clkmgr_csr_rw | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| clkmgr_csr_aliasing | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| clkmgr_same_csr_outstanding | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| tl_intg_err | 0 | 2 | 0.00 | |||
| clkmgr_sec_cm | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| clkmgr_tl_intg_err | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| shadow_reg_update_error | 0 | 1 | 0.00 | |||
| clkmgr_shadow_reg_errors | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| shadow_reg_read_clear_staged_value | 0 | 1 | 0.00 | |||
| clkmgr_shadow_reg_errors | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| shadow_reg_storage_error | 0 | 1 | 0.00 | |||
| clkmgr_shadow_reg_errors | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| shadowed_reset_glitch | 0 | 1 | 0.00 | |||
| clkmgr_shadow_reg_errors | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| shadow_reg_update_error_with_csr_rw | 0 | 1 | 0.00 | |||
| clkmgr_shadow_reg_errors_with_csr_rw | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| sec_cm_bus_integrity | 0 | 1 | 0.00 | |||
| clkmgr_tl_intg_err | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| sec_cm_meas_clk_bkgn_chk | 0 | 1 | 0.00 | |||
| clkmgr_frequency | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| sec_cm_timeout_clk_bkgn_chk | 0 | 1 | 0.00 | |||
| clkmgr_frequency_timeout | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| sec_cm_meas_config_shadow | 0 | 1 | 0.00 | |||
| clkmgr_shadow_reg_errors | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| sec_cm_idle_intersig_mubi | 0 | 1 | 0.00 | |||
| clkmgr_idle_intersig_mubi | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| sec_cm_jitter_config_mubi | 0 | 1 | 0.00 | |||
| clkmgr_csr_rw | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| sec_cm_idle_ctr_redun | 0 | 1 | 0.00 | |||
| clkmgr_sec_cm | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| sec_cm_meas_config_regwen | 0 | 1 | 0.00 | |||
| clkmgr_csr_rw | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| sec_cm_clk_ctrl_config_regwen | 0 | 1 | 0.00 | |||
| clkmgr_csr_rw | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| prim_count_check | 0 | 1 | 0.00 | |||
| clkmgr_sec_cm | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| regwen | 0 | 1 | 0.00 | |||
| clkmgr_regwen | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| stress_all_with_rand_reset | 0 | 1 | 0.00 | |||
| clkmgr_stress_all_with_rand_reset | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| Test | seed | line | log context | |
|---|---|---|---|---|
| xmvlog: *E,ENUMERR (src/lowrisc_darjeeling_dv_clkmgr_env_*/seq_lib/clkmgr_regwen_vseq.sv,*|52): This assignment is a violation of SystemVerilog strong typing rules for enumeration datatypes. | ||||
| default | None | 1003 |
xmvlog: *E,ENUMERR (src/lowrisc_darjeeling_dv_clkmgr_env_0.1/seq_lib/clkmgr_regwen_vseq.sv,21|52): This assignment is a violation of SystemVerilog strong typing rules for enumeration datatypes.
package worklib.clkmgr_env_pkg:sv
errors: 1, warnings: 2
file: src/lowrisc_darjeeling_dv_clkmgr_env_0.1/clkmgr_if.sv
import clkmgr_env_pkg::*;
|
|
| cover_reg_top | None | 1003 |
xmvlog: *E,ENUMERR (src/lowrisc_darjeeling_dv_clkmgr_env_0.1/seq_lib/clkmgr_regwen_vseq.sv,21|52): This assignment is a violation of SystemVerilog strong typing rules for enumeration datatypes.
package worklib.clkmgr_env_pkg:sv
errors: 1, warnings: 2
file: src/lowrisc_darjeeling_dv_clkmgr_env_0.1/clkmgr_if.sv
import clkmgr_env_pkg::*;
|
|
| Job killed most likely because its dependent job failed. | ||||
| clkmgr_smoke | 62634047826107204864093845041311674550314071441182804480789986306278134911610 | None | ||
| clkmgr_frequency | 13018357105459744581723111234898277966700269930658992575799125521623017061015 | None | ||
| clkmgr_frequency_timeout | 44359369069872175757924909860964056143771457965035681548941360214318319079397 | None | ||
| clkmgr_peri | 23236267596863905418774679212762813522916121375713076029851176499520414284624 | None | ||
| clkmgr_trans | 84563568365034715362383915401813119707500999055313614242851408497836052594905 | None | ||
| clkmgr_clk_status | 19559857449889517445969807755038402799779552102307322367373464218309389723828 | None | ||
| clkmgr_idle_intersig_mubi | 5040972328746047847858040499015263705620781950516084098229513552288546531718 | None | ||
| clkmgr_regwen | 111056919012522030983273770408730176948975416941977142258916680680245902644975 | None | ||
| clkmgr_sec_cm | 3029853440969052849049561423412866242009634775494094906476704392241576446727 | None | ||
| clkmgr_stress_all_with_rand_reset | 73881081214433138480961250658200300702026882917818626125759766084003473717903 | None | ||
| clkmgr_stress_all | 47948794956522989512817399834943333689525764705785067882818510064233103777831 | None | ||
| clkmgr_alert_test | 97433979055403138629639689099504122750752794826105531896273517597162632130442 | None | ||
| clkmgr_shadow_reg_errors | 4719907927896128093918174288967004373672313503462353682921879103698947330453 | None | ||
| clkmgr_shadow_reg_errors_with_csr_rw | 55636766908763916134054676806137573624237810232254270274342733617521977833371 | None | ||
| clkmgr_tl_errors | 41956747430150724979725667873461987928795604685826713058838547661171825989174 | None | ||
| clkmgr_tl_intg_err | 111659273324346320465868150541918006526048577663763607077091879846616963971934 | None | ||
| clkmgr_csr_hw_reset | 57340449530131468996065049621586852117776419478437350507087433649614451323305 | None | ||
| clkmgr_csr_rw | 38191585664133421749229168078840364131149569970615192429266340653167347110079 | None | ||
| clkmgr_csr_bit_bash | 97026202627744916864979329307893918460686970891408376029637418728929085115002 | None | ||
| clkmgr_csr_aliasing | 87420639701260102011170123210015741298192791947486761780467831913102050073556 | None | ||
| clkmgr_same_csr_outstanding | 23013571157681087450677130038204091616877841535706566761090521179743526898528 | None | ||
| clkmgr_csr_mem_rw_with_rand_reset | 107162428686938317531751098035397798690089144270762935920362224222066160225983 | None | ||
| clkmgr | None | None | ||
| clkmgr | None | None | ||