Simulation Results: csrng

 
07/04/2026 16:08:41 DVSim: v1.17.3 sha: ae672c6 json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 88.81 %
  • code
  • 92.31 %
  • assert
  • 93.23 %
  • func
  • 80.89 %
  • block
  • 96.98 %
  • line
  • 97.80 %
  • branch
  • 92.42 %
  • toggle
  • 93.31 %
  • FSM
  • 85.71 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
V3
0.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
csrng_smoke 2.000s 53.590us 1 1 100.00
csr_hw_reset 1 1 100.00
csrng_csr_hw_reset 2.000s 18.205us 1 1 100.00
csr_rw 1 1 100.00
csrng_csr_rw 3.000s 73.342us 1 1 100.00
csr_bit_bash 1 1 100.00
csrng_csr_bit_bash 4.000s 102.986us 1 1 100.00
csr_aliasing 1 1 100.00
csrng_csr_aliasing 4.000s 73.442us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
csrng_csr_mem_rw_with_rand_reset 2.000s 17.224us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
csrng_csr_rw 3.000s 73.342us 1 1 100.00
csrng_csr_aliasing 4.000s 73.442us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
interrupts 1 1 100.00
csrng_intr 5.000s 206.085us 1 1 100.00
alerts 1 1 100.00
csrng_alert 8.000s 215.226us 1 1 100.00
err 1 1 100.00
csrng_err 2.000s 26.917us 1 1 100.00
cmds 1 1 100.00
csrng_cmds 11.000s 513.054us 1 1 100.00
life cycle 1 1 100.00
csrng_cmds 11.000s 513.054us 1 1 100.00
stress_all 1 1 100.00
csrng_stress_all 492.000s 49138.724us 1 1 100.00
intr_test 1 1 100.00
csrng_intr_test 2.000s 11.975us 1 1 100.00
alert_test 1 1 100.00
csrng_alert_test 2.000s 58.619us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
csrng_tl_errors 7.000s 567.279us 1 1 100.00
tl_d_illegal_access 1 1 100.00
csrng_tl_errors 7.000s 567.279us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
csrng_csr_hw_reset 2.000s 18.205us 1 1 100.00
csrng_csr_rw 3.000s 73.342us 1 1 100.00
csrng_csr_aliasing 4.000s 73.442us 1 1 100.00
csrng_same_csr_outstanding 6.000s 464.432us 1 1 100.00
tl_d_partial_access 4 4 100.00
csrng_csr_hw_reset 2.000s 18.205us 1 1 100.00
csrng_csr_rw 3.000s 73.342us 1 1 100.00
csrng_csr_aliasing 4.000s 73.442us 1 1 100.00
csrng_same_csr_outstanding 6.000s 464.432us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
csrng_tl_intg_err 7.000s 398.597us 1 1 100.00
csrng_sec_cm 4.000s 422.984us 1 1 100.00
sec_cm_config_regwen 2 2 100.00
csrng_csr_rw 3.000s 73.342us 1 1 100.00
csrng_regwen 2.000s 26.115us 1 1 100.00
sec_cm_config_mubi 1 1 100.00
csrng_alert 8.000s 215.226us 1 1 100.00
sec_cm_intersig_mubi 1 1 100.00
csrng_stress_all 492.000s 49138.724us 1 1 100.00
sec_cm_main_sm_fsm_sparse 3 3 100.00
csrng_intr 5.000s 206.085us 1 1 100.00
csrng_err 2.000s 26.917us 1 1 100.00
csrng_sec_cm 4.000s 422.984us 1 1 100.00
sec_cm_cmd_stage_fsm_sparse 3 3 100.00
csrng_intr 5.000s 206.085us 1 1 100.00
csrng_err 2.000s 26.917us 1 1 100.00
csrng_sec_cm 4.000s 422.984us 1 1 100.00
sec_cm_ctr_drbg_fsm_sparse 3 3 100.00
csrng_intr 5.000s 206.085us 1 1 100.00
csrng_err 2.000s 26.917us 1 1 100.00
csrng_sec_cm 4.000s 422.984us 1 1 100.00
sec_cm_ctr_drbg_ctr_redun 3 3 100.00
csrng_intr 5.000s 206.085us 1 1 100.00
csrng_err 2.000s 26.917us 1 1 100.00
csrng_sec_cm 4.000s 422.984us 1 1 100.00
sec_cm_gen_cmd_ctr_redun 3 3 100.00
csrng_intr 5.000s 206.085us 1 1 100.00
csrng_err 2.000s 26.917us 1 1 100.00
csrng_sec_cm 4.000s 422.984us 1 1 100.00
sec_cm_ctrl_mubi 1 1 100.00
csrng_alert 8.000s 215.226us 1 1 100.00
sec_cm_main_sm_ctr_local_esc 2 2 100.00
csrng_intr 5.000s 206.085us 1 1 100.00
csrng_err 2.000s 26.917us 1 1 100.00
sec_cm_constants_lc_gated 1 1 100.00
csrng_stress_all 492.000s 49138.724us 1 1 100.00
sec_cm_sw_genbits_bus_consistency 1 1 100.00
csrng_alert 8.000s 215.226us 1 1 100.00
sec_cm_tile_link_bus_integrity 1 1 100.00
csrng_tl_intg_err 7.000s 398.597us 1 1 100.00
sec_cm_aes_cipher_fsm_sparse 3 3 100.00
csrng_intr 5.000s 206.085us 1 1 100.00
csrng_err 2.000s 26.917us 1 1 100.00
csrng_sec_cm 4.000s 422.984us 1 1 100.00
sec_cm_aes_cipher_fsm_redun 2 2 100.00
csrng_intr 5.000s 206.085us 1 1 100.00
csrng_err 2.000s 26.917us 1 1 100.00
sec_cm_aes_cipher_ctrl_sparse 2 2 100.00
csrng_intr 5.000s 206.085us 1 1 100.00
csrng_err 2.000s 26.917us 1 1 100.00
sec_cm_aes_cipher_fsm_local_esc 2 2 100.00
csrng_intr 5.000s 206.085us 1 1 100.00
csrng_err 2.000s 26.917us 1 1 100.00
sec_cm_aes_cipher_ctr_redun 3 3 100.00
csrng_intr 5.000s 206.085us 1 1 100.00
csrng_err 2.000s 26.917us 1 1 100.00
csrng_sec_cm 4.000s 422.984us 1 1 100.00
sec_cm_aes_cipher_data_reg_local_esc 2 2 100.00
csrng_intr 5.000s 206.085us 1 1 100.00
csrng_err 2.000s 26.917us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 0 1 0.00
csrng_stress_all_with_rand_reset 0.000s 0.000us 0 1 0.00

Error Messages

   Test seed line log context
Job timed out after * minutes
csrng_stress_all_with_rand_reset 36761718834462868308754031966888582540373876241125608827057616829545455966167 None
Job timed out after 180 minutes