Simulation Results: dma

 
07/04/2026 16:08:41 DVSim: v1.17.3 sha: ae672c6 json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 82.61 %
  • code
  • 91.50 %
  • assert
  • 95.55 %
  • func
  • 60.80 %
  • block
  • 97.38 %
  • line
  • 96.89 %
  • branch
  • 95.83 %
  • toggle
  • 83.12 %
  • FSM
  • 90.14 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
unmapped
66.67%
Testpoint Test Max Runtime Sim Time Pass Total %
dma_memory_smoke 1 1 100.00
dma_memory_smoke 6.000s 582.736us 1 1 100.00
dma_handshake_smoke 1 1 100.00
dma_handshake_smoke 4.000s 1097.337us 1 1 100.00
dma_generic_smoke 1 1 100.00
dma_generic_smoke 6.000s 3002.413us 1 1 100.00
csr_hw_reset 1 1 100.00
dma_csr_hw_reset 2.000s 52.428us 1 1 100.00
csr_rw 1 1 100.00
dma_csr_rw 1.000s 49.255us 1 1 100.00
csr_bit_bash 1 1 100.00
dma_csr_bit_bash 6.000s 2011.781us 1 1 100.00
csr_aliasing 1 1 100.00
dma_csr_aliasing 4.000s 272.168us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
dma_csr_mem_rw_with_rand_reset 2.000s 16.931us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
dma_csr_rw 1.000s 49.255us 1 1 100.00
dma_csr_aliasing 4.000s 272.168us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
dma_memory_region_lock 1 1 100.00
dma_memory_region_lock 53.000s 38082.159us 1 1 100.00
dma_memory_tl_error 1 1 100.00
dma_memory_stress 542.000s 54193.828us 1 1 100.00
dma_handshake_tl_error 1 1 100.00
dma_handshake_stress 168.000s 100931.988us 1 1 100.00
dma_handshake_stress 1 1 100.00
dma_handshake_stress 168.000s 100931.988us 1 1 100.00
dma_memory_stress 1 1 100.00
dma_memory_stress 542.000s 54193.828us 1 1 100.00
dma_generic_stress 1 1 100.00
dma_generic_stress 333.000s 31940.892us 1 1 100.00
dma_handshake_mem_buffer_overflow 1 1 100.00
dma_handshake_stress 168.000s 100931.988us 1 1 100.00
dma_abort 1 1 100.00
dma_abort 8.000s 1661.912us 1 1 100.00
dma_stress_all 1 1 100.00
dma_stress_all 68.000s 6640.838us 1 1 100.00
alert_test 1 1 100.00
dma_alert_test 1.000s 36.692us 1 1 100.00
intr_test 1 1 100.00
dma_intr_test 1.000s 55.747us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
dma_tl_errors 2.000s 273.803us 1 1 100.00
tl_d_illegal_access 1 1 100.00
dma_tl_errors 2.000s 273.803us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
dma_csr_hw_reset 2.000s 52.428us 1 1 100.00
dma_csr_rw 1.000s 49.255us 1 1 100.00
dma_csr_aliasing 4.000s 272.168us 1 1 100.00
dma_same_csr_outstanding 3.000s 57.101us 1 1 100.00
tl_d_partial_access 4 4 100.00
dma_csr_hw_reset 2.000s 52.428us 1 1 100.00
dma_csr_rw 1.000s 49.255us 1 1 100.00
dma_csr_aliasing 4.000s 272.168us 1 1 100.00
dma_same_csr_outstanding 3.000s 57.101us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
dma_illegal_addr_range 3 3 100.00
dma_mem_enabled 13.000s 387.170us 1 1 100.00
dma_generic_stress 333.000s 31940.892us 1 1 100.00
dma_handshake_stress 168.000s 100931.988us 1 1 100.00
dma_config_lock 1 1 100.00
dma_config_lock 6.000s 1267.821us 1 1 100.00
tl_intg_err 2 2 100.00
dma_sec_cm 1.000s 54.002us 1 1 100.00
dma_tl_intg_err 2.000s 193.844us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
Unmapped 2 3 66.67
dma_short_transfer 64.000s 3302.428us 1 1 100.00
dma_longer_transfer 6.000s 269.797us 1 1 100.00
dma_stress_all_with_rand_reset 3.000s 112.601us 0 1 0.00

Error Messages

   Test seed line log context
UVM_ERROR @ *ps: (cip_base_vseq.sv:1237) [dma_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses.
dma_stress_all_with_rand_reset 7985991990179111423194411579029555616827218457633611729928308219882969090817 93
UVM_ERROR @ 112601347ps: (cip_base_vseq.sv:1237) [uvm_test_top.env.virtual_sequencer.dma_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 112601347ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---