Simulation Results: edn/edn0

 
07/04/2026 16:08:41 DVSim: v1.17.3 sha: ae672c6 json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 77.27 %
  • code
  • 87.69 %
  • assert
  • 95.58 %
  • func
  • 48.53 %
  • block
  • 94.90 %
  • line
  • 97.51 %
  • branch
  • 88.97 %
  • toggle
  • 76.68 %
  • FSM
  • 87.60 %
Validation stages
V1
100.00%
V2
92.86%
V2S
100.00%
V3
0.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
edn_smoke 1.000s 48.829us 1 1 100.00
csr_hw_reset 1 1 100.00
edn_csr_hw_reset 2.000s 53.349us 1 1 100.00
csr_rw 1 1 100.00
edn_csr_rw 2.000s 14.364us 1 1 100.00
csr_bit_bash 1 1 100.00
edn_csr_bit_bash 2.000s 94.839us 1 1 100.00
csr_aliasing 1 1 100.00
edn_csr_aliasing 2.000s 96.278us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
edn_csr_mem_rw_with_rand_reset 1.000s 19.206us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
edn_csr_rw 2.000s 14.364us 1 1 100.00
edn_csr_aliasing 2.000s 96.278us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
firmware 1 1 100.00
edn_genbits 1.000s 43.198us 1 1 100.00
csrng_commands 1 1 100.00
edn_genbits 1.000s 43.198us 1 1 100.00
genbits 1 1 100.00
edn_genbits 1.000s 43.198us 1 1 100.00
interrupts 1 1 100.00
edn_intr 2.000s 26.604us 1 1 100.00
alerts 1 1 100.00
edn_alert 1.000s 43.592us 1 1 100.00
errs 0 1 0.00
edn_err 1.000s 3.876us 0 1 0.00
disable 2 2 100.00
edn_disable 1.000s 10.694us 1 1 100.00
edn_disable_auto_req_mode 2.000s 40.137us 1 1 100.00
stress_all 1 1 100.00
edn_stress_all 3.000s 155.973us 1 1 100.00
intr_test 1 1 100.00
edn_intr_test 2.000s 15.828us 1 1 100.00
alert_test 1 1 100.00
edn_alert_test 2.000s 38.604us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
edn_tl_errors 4.000s 643.405us 1 1 100.00
tl_d_illegal_access 1 1 100.00
edn_tl_errors 4.000s 643.405us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
edn_csr_hw_reset 2.000s 53.349us 1 1 100.00
edn_csr_rw 2.000s 14.364us 1 1 100.00
edn_csr_aliasing 2.000s 96.278us 1 1 100.00
edn_same_csr_outstanding 1.000s 48.374us 1 1 100.00
tl_d_partial_access 4 4 100.00
edn_csr_hw_reset 2.000s 53.349us 1 1 100.00
edn_csr_rw 2.000s 14.364us 1 1 100.00
edn_csr_aliasing 2.000s 96.278us 1 1 100.00
edn_same_csr_outstanding 1.000s 48.374us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
edn_sec_cm 5.000s 284.457us 1 1 100.00
edn_tl_intg_err 8.000s 712.092us 1 1 100.00
sec_cm_config_regwen 1 1 100.00
edn_regwen 1.000s 27.433us 1 1 100.00
sec_cm_config_mubi 1 1 100.00
edn_alert 1.000s 43.592us 1 1 100.00
sec_cm_main_sm_fsm_sparse 1 1 100.00
edn_sec_cm 5.000s 284.457us 1 1 100.00
sec_cm_ack_sm_fsm_sparse 1 1 100.00
edn_sec_cm 5.000s 284.457us 1 1 100.00
sec_cm_fifo_ctr_redun 1 1 100.00
edn_sec_cm 5.000s 284.457us 1 1 100.00
sec_cm_ctr_redun 1 1 100.00
edn_sec_cm 5.000s 284.457us 1 1 100.00
sec_cm_main_sm_ctr_local_esc 2 2 100.00
edn_alert 1.000s 43.592us 1 1 100.00
edn_sec_cm 5.000s 284.457us 1 1 100.00
sec_cm_cs_rdata_bus_consistency 1 1 100.00
edn_alert 1.000s 43.592us 1 1 100.00
sec_cm_tile_link_bus_integrity 1 1 100.00
edn_tl_intg_err 8.000s 712.092us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 0 1 0.00
edn_stress_all_with_rand_reset 43.000s 2045.000us 0 1 0.00

Error Messages

   Test seed line log context
UVM_ERROR (cip_base_vseq.sv:1237) [edn_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses.
edn_stress_all_with_rand_reset 58404474127232951033459651018186572347372708518007802060105669815441698411599 162
UVM_ERROR @ 2044999617 ps: (cip_base_vseq.sv:1237) [uvm_test_top.env.virtual_sequencer.edn_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 2044999617 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
xmsim: *E,ASRTST (/nightly/current_run/scratch/master/edn_edn0-sim-xcelium/default/fusesoc-work/src/lowrisc_ip_edn_*/rtl/edn_ack_sm.sv,54): Assertion u_state_regs_A has failed
edn_err 77219472827136743278773600332340849753233251413546035113704543002470283703255 145
xmsim: *E,ASRTST (/nightly/current_run/scratch/master/edn_edn0-sim-xcelium/default/fusesoc-work/src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv,54): (time 3876473 PS) Assertion tb.dut.u_edn_core.gen_ep_blk[0].u_edn_ack_sm_ep.u_state_regs_A has failed
UVM_ERROR @ 3876473 ps: (edn_ack_sm.sv:54) [ASSERT FAILED] u_state_regs_A
UVM_INFO @ 3876473 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---