Simulation Results: hmac

 
07/04/2026 16:08:41 DVSim: v1.17.3 sha: ae672c6 json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 73.67 %
  • code
  • 96.08 %
  • assert
  • 95.86 %
  • func
  • 29.06 %
  • block
  • 97.64 %
  • line
  • 98.44 %
  • branch
  • 94.11 %
  • toggle
  • 96.96 %
  • FSM
  • 94.83 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
V3
100.00%
unmapped
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
hmac_smoke 12.000s 4088.085us 1 1 100.00
csr_hw_reset 1 1 100.00
hmac_csr_hw_reset 1.000s 24.591us 1 1 100.00
csr_rw 1 1 100.00
hmac_csr_rw 1.000s 30.685us 1 1 100.00
csr_bit_bash 1 1 100.00
hmac_csr_bit_bash 8.000s 1459.942us 1 1 100.00
csr_aliasing 1 1 100.00
hmac_csr_aliasing 5.000s 583.503us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
hmac_csr_mem_rw_with_rand_reset 1.000s 19.600us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
hmac_csr_rw 1.000s 30.685us 1 1 100.00
hmac_csr_aliasing 5.000s 583.503us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
long_msg 1 1 100.00
hmac_long_msg 45.000s 35745.405us 1 1 100.00
back_pressure 1 1 100.00
hmac_back_pressure 37.000s 841.100us 1 1 100.00
test_vectors 6 6 100.00
hmac_test_sha256_vectors 188.000s 38439.750us 1 1 100.00
hmac_test_sha384_vectors 426.000s 11533.314us 1 1 100.00
hmac_test_sha512_vectors 435.000s 24650.476us 1 1 100.00
hmac_test_hmac256_vectors 9.000s 261.424us 1 1 100.00
hmac_test_hmac384_vectors 13.000s 720.734us 1 1 100.00
hmac_test_hmac512_vectors 12.000s 1350.930us 1 1 100.00
burst_wr 1 1 100.00
hmac_burst_wr 19.000s 1675.305us 1 1 100.00
datapath_stress 1 1 100.00
hmac_datapath_stress 101.000s 4442.146us 1 1 100.00
error 1 1 100.00
hmac_error 86.000s 6325.696us 1 1 100.00
wipe_secret 1 1 100.00
hmac_wipe_secret 57.000s 3862.860us 1 1 100.00
save_and_restore 6 6 100.00
hmac_smoke 12.000s 4088.085us 1 1 100.00
hmac_long_msg 45.000s 35745.405us 1 1 100.00
hmac_back_pressure 37.000s 841.100us 1 1 100.00
hmac_datapath_stress 101.000s 4442.146us 1 1 100.00
hmac_burst_wr 19.000s 1675.305us 1 1 100.00
hmac_stress_all 127.000s 25444.605us 1 1 100.00
fifo_empty_status_interrupt 11 11 100.00
hmac_smoke 12.000s 4088.085us 1 1 100.00
hmac_long_msg 45.000s 35745.405us 1 1 100.00
hmac_back_pressure 37.000s 841.100us 1 1 100.00
hmac_datapath_stress 101.000s 4442.146us 1 1 100.00
hmac_wipe_secret 57.000s 3862.860us 1 1 100.00
hmac_test_sha256_vectors 188.000s 38439.750us 1 1 100.00
hmac_test_sha384_vectors 426.000s 11533.314us 1 1 100.00
hmac_test_sha512_vectors 435.000s 24650.476us 1 1 100.00
hmac_test_hmac256_vectors 9.000s 261.424us 1 1 100.00
hmac_test_hmac384_vectors 13.000s 720.734us 1 1 100.00
hmac_test_hmac512_vectors 12.000s 1350.930us 1 1 100.00
wide_digest_configurable_key_length 14 14 100.00
hmac_smoke 12.000s 4088.085us 1 1 100.00
hmac_long_msg 45.000s 35745.405us 1 1 100.00
hmac_back_pressure 37.000s 841.100us 1 1 100.00
hmac_datapath_stress 101.000s 4442.146us 1 1 100.00
hmac_burst_wr 19.000s 1675.305us 1 1 100.00
hmac_error 86.000s 6325.696us 1 1 100.00
hmac_wipe_secret 57.000s 3862.860us 1 1 100.00
hmac_test_sha256_vectors 188.000s 38439.750us 1 1 100.00
hmac_test_sha384_vectors 426.000s 11533.314us 1 1 100.00
hmac_test_sha512_vectors 435.000s 24650.476us 1 1 100.00
hmac_test_hmac256_vectors 9.000s 261.424us 1 1 100.00
hmac_test_hmac384_vectors 13.000s 720.734us 1 1 100.00
hmac_test_hmac512_vectors 12.000s 1350.930us 1 1 100.00
hmac_stress_all 127.000s 25444.605us 1 1 100.00
stress_all 1 1 100.00
hmac_stress_all 127.000s 25444.605us 1 1 100.00
alert_test 1 1 100.00
hmac_alert_test 2.000s 13.461us 1 1 100.00
intr_test 1 1 100.00
hmac_intr_test 1.000s 190.272us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
hmac_tl_errors 3.000s 424.313us 1 1 100.00
tl_d_illegal_access 1 1 100.00
hmac_tl_errors 3.000s 424.313us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
hmac_csr_hw_reset 1.000s 24.591us 1 1 100.00
hmac_csr_rw 1.000s 30.685us 1 1 100.00
hmac_csr_aliasing 5.000s 583.503us 1 1 100.00
hmac_same_csr_outstanding 1.000s 44.707us 1 1 100.00
tl_d_partial_access 4 4 100.00
hmac_csr_hw_reset 1.000s 24.591us 1 1 100.00
hmac_csr_rw 1.000s 30.685us 1 1 100.00
hmac_csr_aliasing 5.000s 583.503us 1 1 100.00
hmac_same_csr_outstanding 1.000s 44.707us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
hmac_tl_intg_err 2.000s 81.668us 1 1 100.00
hmac_sec_cm 1.000s 141.465us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
hmac_tl_intg_err 2.000s 81.668us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
write_config_and_secret_key_during_msg_wr 1 1 100.00
hmac_smoke 12.000s 4088.085us 1 1 100.00
stress_reset 1 1 100.00
hmac_stress_reset 3.000s 75.651us 1 1 100.00
stress_all_with_rand_reset 1 1 100.00
hmac_stress_all_with_rand_reset 75.000s 4445.168us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
Unmapped 1 1 100.00
hmac_directed 7.000s 19.787us 1 1 100.00