Simulation Results: i2c

 
07/04/2026 16:08:41 DVSim: v1.17.3 sha: ae672c6 json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 88.49 %
  • code
  • 89.22 %
  • assert
  • 96.19 %
  • func
  • 80.07 %
  • block
  • 95.93 %
  • line
  • 95.26 %
  • branch
  • 92.69 %
  • toggle
  • 86.90 %
  • FSM
  • 82.01 %
Validation stages
V1
100.00%
V2
82.93%
V2S
100.00%
V3
0.00%
Testpoint Test Max Runtime Sim Time Pass Total %
host_smoke 1 1 100.00
i2c_host_smoke 20.000s 2389.438us 1 1 100.00
target_smoke 1 1 100.00
i2c_target_smoke 20.000s 1243.121us 1 1 100.00
csr_hw_reset 1 1 100.00
i2c_csr_hw_reset 1.000s 22.723us 1 1 100.00
csr_rw 1 1 100.00
i2c_csr_rw 1.000s 47.022us 1 1 100.00
csr_bit_bash 1 1 100.00
i2c_csr_bit_bash 4.000s 114.466us 1 1 100.00
csr_aliasing 1 1 100.00
i2c_csr_aliasing 2.000s 426.635us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
i2c_csr_mem_rw_with_rand_reset 1.000s 26.368us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
i2c_csr_rw 1.000s 47.022us 1 1 100.00
i2c_csr_aliasing 2.000s 426.635us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
host_error_intr 0 1 0.00
i2c_host_error_intr 1.000s 57.139us 0 1 0.00
host_stress_all 0 1 0.00
i2c_host_stress_all 0.000s 0.000us 0 1 0.00
host_maxperf 1 1 100.00
i2c_host_perf 811.000s 5478.502us 1 1 100.00
host_override 1 1 100.00
i2c_host_override 2.000s 18.838us 1 1 100.00
host_fifo_watermark 0 1 0.00
i2c_host_fifo_watermark 0.000s 0.000us 0 1 0.00
host_fifo_overflow 1 1 100.00
i2c_host_fifo_overflow 257.000s 5467.736us 1 1 100.00
host_fifo_reset 3 3 100.00
i2c_host_fifo_reset_fmt 2.000s 104.918us 1 1 100.00
i2c_host_fifo_fmt_empty 29.000s 1036.301us 1 1 100.00
i2c_host_fifo_reset_rx 4.000s 732.060us 1 1 100.00
host_fifo_full 1 1 100.00
i2c_host_fifo_full 39.000s 3381.640us 1 1 100.00
host_timeout 1 1 100.00
i2c_host_stretch_timeout 15.000s 2786.745us 1 1 100.00
i2c_host_mode_toggle 0 1 0.00
i2c_host_mode_toggle 2.000s 352.016us 0 1 0.00
target_glitch 0 1 0.00
i2c_target_glitch 4.000s 4372.087us 0 1 0.00
target_stress_all 1 1 100.00
i2c_target_stress_all 3544.000s 122876.178us 1 1 100.00
target_maxperf 1 1 100.00
i2c_target_perf 4.000s 563.108us 1 1 100.00
target_fifo_empty 2 2 100.00
i2c_target_stress_rd 11.000s 378.815us 1 1 100.00
i2c_target_intr_smoke 4.000s 6740.306us 1 1 100.00
target_fifo_reset 2 2 100.00
i2c_target_fifo_reset_acq 2.000s 632.771us 1 1 100.00
i2c_target_fifo_reset_tx 2.000s 766.638us 1 1 100.00
target_fifo_full 1 3 33.33
i2c_target_stress_wr 0.000s 0.000us 0 1 0.00
i2c_target_stress_rd 11.000s 378.815us 1 1 100.00
i2c_target_intr_stress_wr 0.000s 0.000us 0 1 0.00
target_timeout 1 1 100.00
i2c_target_timeout 8.000s 4280.057us 1 1 100.00
target_clock_stretch 1 1 100.00
i2c_target_stretch 45.000s 1396.260us 1 1 100.00
bad_address 1 1 100.00
i2c_target_bad_addr 5.000s 2127.651us 1 1 100.00
target_mode_glitch 1 1 100.00
i2c_target_hrst 2.000s 3282.701us 1 1 100.00
target_fifo_watermark 2 2 100.00
i2c_target_fifo_watermarks_acq 4.000s 2579.998us 1 1 100.00
i2c_target_fifo_watermarks_tx 2.000s 663.650us 1 1 100.00
host_mode_config_perf 2 2 100.00
i2c_host_perf 811.000s 5478.502us 1 1 100.00
i2c_host_perf_precise 2.000s 41.577us 1 1 100.00
host_mode_clock_stretching 1 1 100.00
i2c_host_stretch_timeout 15.000s 2786.745us 1 1 100.00
target_mode_tx_stretch_ctrl 1 1 100.00
i2c_target_tx_stretch_ctrl 3.000s 123.156us 1 1 100.00
target_mode_nack_generation 3 3 100.00
i2c_target_nack_acqfull 3.000s 2065.917us 1 1 100.00
i2c_target_nack_acqfull_addr 3.000s 491.038us 1 1 100.00
i2c_target_nack_txstretch 3.000s 466.646us 1 1 100.00
host_mode_halt_on_nak 1 1 100.00
i2c_host_may_nack 14.000s 866.694us 1 1 100.00
target_mode_smbus_maxlen 1 1 100.00
i2c_target_smbus_maxlen 3.000s 2121.164us 1 1 100.00
alert_test 1 1 100.00
i2c_alert_test 2.000s 17.643us 1 1 100.00
intr_test 1 1 100.00
i2c_intr_test 2.000s 28.261us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
i2c_tl_errors 2.000s 45.840us 1 1 100.00
tl_d_illegal_access 1 1 100.00
i2c_tl_errors 2.000s 45.840us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
i2c_csr_hw_reset 1.000s 22.723us 1 1 100.00
i2c_csr_rw 1.000s 47.022us 1 1 100.00
i2c_csr_aliasing 2.000s 426.635us 1 1 100.00
i2c_same_csr_outstanding 2.000s 34.884us 1 1 100.00
tl_d_partial_access 4 4 100.00
i2c_csr_hw_reset 1.000s 22.723us 1 1 100.00
i2c_csr_rw 1.000s 47.022us 1 1 100.00
i2c_csr_aliasing 2.000s 426.635us 1 1 100.00
i2c_same_csr_outstanding 2.000s 34.884us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
i2c_sec_cm 2.000s 165.740us 1 1 100.00
i2c_tl_intg_err 2.000s 312.265us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
i2c_tl_intg_err 2.000s 312.265us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
host_stress_all_with_rand_reset 0 1 0.00
i2c_host_stress_all_with_rand_reset 16.000s 2127.351us 0 1 0.00
target_error_intr 0 1 0.00
i2c_target_unexp_stop 2.000s 15.944us 0 1 0.00
target_stress_all_with_rand_reset 0 1 0.00
i2c_target_stress_all_with_rand_reset 9.000s 556.623us 0 1 0.00

Error Messages

   Test seed line log context
Job timed out after * minutes
i2c_host_fifo_watermark 43176848170215361774821065614075603881746012265590877497152097021765689874785 None
Job timed out after 60 minutes
i2c_host_stress_all 18348761288243241764991081213600169470998823112438361933434985772395554158399 None
Job timed out after 60 minutes
i2c_target_stress_wr 103774063967334201117230359036805204118038124286764834760696202842304096559760 None
Job timed out after 60 minutes
i2c_target_intr_stress_wr 56135153292949945757567979172925519888610466237006283337411889104963595543246 None
Job timed out after 60 minutes
UVM_ERROR sequencer [sequencer] Get_next_item called twice without item_done or get in between
i2c_host_error_intr 13369660099970454663005004466229423198570275462963027947691833249508391695718 92
UVM_ERROR @ 57138756 ps: uvm_test_top.env.m_i2c_agent.sequencer [uvm_test_top.env.m_i2c_agent.sequencer] Get_next_item called twice without item_done or get in between
UVM_INFO @ 57138756 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR sequencer [sequencer] get_next_item/try_next_item called twice without item_done or get in between
i2c_target_glitch 88062050232534745056294125173663307903055463674078566110576181843119930516911 93
UVM_ERROR @ 4372087001 ps: uvm_test_top.env.m_i2c_agent.sequencer [uvm_test_top.env.m_i2c_agent.sequencer] get_next_item/try_next_item called twice without item_done or get in between
UVM_INFO @ 4372087001 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (i2c_scoreboard.sv:682) [scoreboard] Check failed obs.data_q[i] == exp.data_q[i] (* [*] vs * [*])
i2c_target_unexp_stop 112844907329104927344478858321482974859901251863206519584614508933348683978741 87
UVM_ERROR @ 15943859 ps: (i2c_scoreboard.sv:682) [uvm_test_top.env.scoreboard] Check failed obs.data_q[i] == exp.data_q[i] (255 [0xff] vs 161 [0xa1])
UVM_INFO @ 15943859 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_vseq.sv:1237) [i2c_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses.
i2c_host_stress_all_with_rand_reset 109878108465775455864505070895694068694128471178639800806841261673650757258830 108
UVM_ERROR @ 2127350576 ps: (cip_base_vseq.sv:1237) [uvm_test_top.env.virtual_sequencer.i2c_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 2127350576 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_vseq.sv:1150) [i2c_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
i2c_target_stress_all_with_rand_reset 40228664182638492943696500577578742220102838599986061040023073414521907969421 94
UVM_ERROR @ 556622893 ps: (cip_base_vseq.sv:1150) [uvm_test_top.env.virtual_sequencer.i2c_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
UVM_INFO @ 556622893 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (i2c_scoreboard.sv:716) [scoreboard] controller_mode_rd_obs_fifo item uncompared:
i2c_host_mode_toggle 111843509358649262606180302260630003715200726821823881139420779285298059621962 94
UVM_ERROR @ 352015878 ps: (i2c_scoreboard.sv:716) [uvm_test_top.env.scoreboard] controller_mode_rd_obs_fifo item uncompared:
----------------------------------------------------
Name Type Size Value
----------------------------------------------------
mon_dut_item i2c_item - @16494