Simulation Results: lc_ctrl/volatile_unlock_disabled

 
07/04/2026 16:08:41 DVSim: v1.17.3 sha: ae672c6 json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 91.64 %
  • code
  • 93.28 %
  • assert
  • 95.97 %
  • func
  • 85.67 %
  • block
  • 96.70 %
  • line
  • 97.35 %
  • branch
  • 91.61 %
  • toggle
  • 88.90 %
  • FSM
  • 95.24 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
V3
0.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
lc_ctrl_smoke 2.000s 38.609us 1 1 100.00
csr_hw_reset 1 1 100.00
lc_ctrl_csr_hw_reset 1.000s 20.580us 1 1 100.00
csr_rw 1 1 100.00
lc_ctrl_csr_rw 1.000s 12.627us 1 1 100.00
csr_bit_bash 1 1 100.00
lc_ctrl_csr_bit_bash 2.000s 52.299us 1 1 100.00
csr_aliasing 1 1 100.00
lc_ctrl_csr_aliasing 2.000s 153.860us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
lc_ctrl_csr_mem_rw_with_rand_reset 1.000s 74.334us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
lc_ctrl_csr_rw 1.000s 12.627us 1 1 100.00
lc_ctrl_csr_aliasing 2.000s 153.860us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
state_post_trans 1 1 100.00
lc_ctrl_state_post_trans 2.000s 772.681us 1 1 100.00
regwen_during_op 1 1 100.00
lc_ctrl_regwen_during_op 8.000s 232.536us 1 1 100.00
rand_wr_claim_transition_if 1 1 100.00
lc_ctrl_claim_transition_if 2.000s 14.842us 1 1 100.00
lc_prog_failure 1 1 100.00
lc_ctrl_prog_failure 3.000s 68.590us 1 1 100.00
lc_state_failure 1 1 100.00
lc_ctrl_state_failure 5.000s 180.694us 1 1 100.00
lc_errors 1 1 100.00
lc_ctrl_errors 5.000s 1518.555us 1 1 100.00
security_escalation 7 7 100.00
lc_ctrl_state_failure 5.000s 180.694us 1 1 100.00
lc_ctrl_prog_failure 3.000s 68.590us 1 1 100.00
lc_ctrl_errors 5.000s 1518.555us 1 1 100.00
lc_ctrl_security_escalation 5.000s 426.472us 1 1 100.00
lc_ctrl_jtag_state_failure 69.000s 9310.149us 1 1 100.00
lc_ctrl_jtag_prog_failure 4.000s 1495.555us 1 1 100.00
lc_ctrl_jtag_errors 59.000s 10236.551us 1 1 100.00
jtag_access 13 13 100.00
lc_ctrl_jtag_smoke 5.000s 878.873us 1 1 100.00
lc_ctrl_jtag_state_post_trans 12.000s 1746.037us 1 1 100.00
lc_ctrl_jtag_prog_failure 4.000s 1495.555us 1 1 100.00
lc_ctrl_jtag_errors 59.000s 10236.551us 1 1 100.00
lc_ctrl_jtag_access 7.000s 856.924us 1 1 100.00
lc_ctrl_jtag_regwen_during_op 22.000s 5738.193us 1 1 100.00
lc_ctrl_jtag_csr_hw_reset 3.000s 87.976us 1 1 100.00
lc_ctrl_jtag_csr_rw 1.000s 97.364us 1 1 100.00
lc_ctrl_jtag_csr_bit_bash 8.000s 388.276us 1 1 100.00
lc_ctrl_jtag_csr_aliasing 3.000s 1161.606us 1 1 100.00
lc_ctrl_jtag_same_csr_outstanding 1.000s 40.008us 1 1 100.00
lc_ctrl_jtag_csr_mem_rw_with_rand_reset 1.000s 303.854us 1 1 100.00
lc_ctrl_jtag_alert_test 2.000s 90.345us 1 1 100.00
jtag_priority 1 1 100.00
lc_ctrl_jtag_priority 3.000s 128.631us 1 1 100.00
lc_ctrl_volatile_unlock 1 1 100.00
lc_ctrl_volatile_unlock_smoke 2.000s 24.870us 1 1 100.00
stress_all 1 1 100.00
lc_ctrl_stress_all 146.000s 16620.758us 1 1 100.00
alert_test 1 1 100.00
lc_ctrl_alert_test 2.000s 25.157us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
lc_ctrl_tl_errors 2.000s 92.353us 1 1 100.00
tl_d_illegal_access 1 1 100.00
lc_ctrl_tl_errors 2.000s 92.353us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
lc_ctrl_csr_hw_reset 1.000s 20.580us 1 1 100.00
lc_ctrl_csr_rw 1.000s 12.627us 1 1 100.00
lc_ctrl_csr_aliasing 2.000s 153.860us 1 1 100.00
lc_ctrl_same_csr_outstanding 2.000s 40.659us 1 1 100.00
tl_d_partial_access 4 4 100.00
lc_ctrl_csr_hw_reset 1.000s 20.580us 1 1 100.00
lc_ctrl_csr_rw 1.000s 12.627us 1 1 100.00
lc_ctrl_csr_aliasing 2.000s 153.860us 1 1 100.00
lc_ctrl_same_csr_outstanding 2.000s 40.659us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
lc_ctrl_sec_cm 2.000s 128.952us 1 1 100.00
lc_ctrl_tl_intg_err 2.000s 224.984us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
lc_ctrl_tl_intg_err 2.000s 224.984us 1 1 100.00
sec_cm_transition_config_regwen 1 1 100.00
lc_ctrl_regwen_during_op 8.000s 232.536us 1 1 100.00
sec_cm_manuf_state_sparse 2 2 100.00
lc_ctrl_state_failure 5.000s 180.694us 1 1 100.00
lc_ctrl_sec_cm 2.000s 128.952us 1 1 100.00
sec_cm_transition_ctr_sparse 2 2 100.00
lc_ctrl_state_failure 5.000s 180.694us 1 1 100.00
lc_ctrl_sec_cm 2.000s 128.952us 1 1 100.00
sec_cm_manuf_state_bkgn_chk 2 2 100.00
lc_ctrl_state_failure 5.000s 180.694us 1 1 100.00
lc_ctrl_sec_cm 2.000s 128.952us 1 1 100.00
sec_cm_transition_ctr_bkgn_chk 2 2 100.00
lc_ctrl_state_failure 5.000s 180.694us 1 1 100.00
lc_ctrl_sec_cm 2.000s 128.952us 1 1 100.00
sec_cm_state_config_sparse 2 2 100.00
lc_ctrl_state_failure 5.000s 180.694us 1 1 100.00
lc_ctrl_sec_cm 2.000s 128.952us 1 1 100.00
sec_cm_main_fsm_sparse 2 2 100.00
lc_ctrl_state_failure 5.000s 180.694us 1 1 100.00
lc_ctrl_sec_cm 2.000s 128.952us 1 1 100.00
sec_cm_kmac_fsm_sparse 2 2 100.00
lc_ctrl_state_failure 5.000s 180.694us 1 1 100.00
lc_ctrl_sec_cm 2.000s 128.952us 1 1 100.00
sec_cm_main_fsm_local_esc 2 2 100.00
lc_ctrl_state_failure 5.000s 180.694us 1 1 100.00
lc_ctrl_sec_cm 2.000s 128.952us 1 1 100.00
sec_cm_main_fsm_global_esc 1 1 100.00
lc_ctrl_security_escalation 5.000s 426.472us 1 1 100.00
sec_cm_main_ctrl_flow_consistency 2 2 100.00
lc_ctrl_state_post_trans 2.000s 772.681us 1 1 100.00
lc_ctrl_jtag_state_post_trans 12.000s 1746.037us 1 1 100.00
sec_cm_intersig_mubi 1 1 100.00
lc_ctrl_sec_mubi 5.000s 525.988us 1 1 100.00
sec_cm_token_valid_ctrl_mubi 1 1 100.00
lc_ctrl_sec_mubi 5.000s 525.988us 1 1 100.00
sec_cm_token_digest 1 1 100.00
lc_ctrl_sec_token_digest 10.000s 4502.640us 1 1 100.00
sec_cm_token_mux_ctrl_redun 1 1 100.00
lc_ctrl_sec_token_mux 6.000s 676.529us 1 1 100.00
sec_cm_token_valid_mux_redun 1 1 100.00
lc_ctrl_sec_token_mux 6.000s 676.529us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 0 1 0.00
lc_ctrl_stress_all_with_rand_reset 31.000s 2915.392us 0 1 0.00

Error Messages

   Test seed line log context
UVM_ERROR (cip_base_vseq.sv:1237) [lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses.
lc_ctrl_stress_all_with_rand_reset 83082453899875437825317859147986345908548493393868298745961341862107779393373 1478
UVM_ERROR @ 2915391973 ps: (cip_base_vseq.sv:1237) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 2915391973 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---