Simulation Results: lc_ctrl/volatile_unlock_enabled

 
07/04/2026 16:08:41 DVSim: v1.17.3 sha: ae672c6 json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 92.08 %
  • code
  • 93.97 %
  • assert
  • 95.97 %
  • func
  • 86.31 %
  • block
  • 96.98 %
  • line
  • 97.51 %
  • branch
  • 92.33 %
  • toggle
  • 88.42 %
  • FSM
  • 97.62 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
V3
0.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
lc_ctrl_smoke 3.000s 237.830us 1 1 100.00
csr_hw_reset 1 1 100.00
lc_ctrl_csr_hw_reset 1.000s 69.279us 1 1 100.00
csr_rw 1 1 100.00
lc_ctrl_csr_rw 2.000s 46.591us 1 1 100.00
csr_bit_bash 1 1 100.00
lc_ctrl_csr_bit_bash 2.000s 62.822us 1 1 100.00
csr_aliasing 1 1 100.00
lc_ctrl_csr_aliasing 2.000s 21.827us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
lc_ctrl_csr_mem_rw_with_rand_reset 2.000s 53.534us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
lc_ctrl_csr_rw 2.000s 46.591us 1 1 100.00
lc_ctrl_csr_aliasing 2.000s 21.827us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
state_post_trans 1 1 100.00
lc_ctrl_state_post_trans 4.000s 407.452us 1 1 100.00
regwen_during_op 1 1 100.00
lc_ctrl_regwen_during_op 4.000s 820.510us 1 1 100.00
rand_wr_claim_transition_if 1 1 100.00
lc_ctrl_claim_transition_if 2.000s 23.637us 1 1 100.00
lc_prog_failure 1 1 100.00
lc_ctrl_prog_failure 3.000s 355.535us 1 1 100.00
lc_state_failure 1 1 100.00
lc_ctrl_state_failure 8.000s 1356.326us 1 1 100.00
lc_errors 1 1 100.00
lc_ctrl_errors 5.000s 871.243us 1 1 100.00
security_escalation 7 7 100.00
lc_ctrl_state_failure 8.000s 1356.326us 1 1 100.00
lc_ctrl_prog_failure 3.000s 355.535us 1 1 100.00
lc_ctrl_errors 5.000s 871.243us 1 1 100.00
lc_ctrl_security_escalation 5.000s 633.804us 1 1 100.00
lc_ctrl_jtag_state_failure 26.000s 1453.283us 1 1 100.00
lc_ctrl_jtag_prog_failure 6.000s 1723.219us 1 1 100.00
lc_ctrl_jtag_errors 17.000s 2425.651us 1 1 100.00
jtag_access 13 13 100.00
lc_ctrl_jtag_smoke 4.000s 639.146us 1 1 100.00
lc_ctrl_jtag_state_post_trans 10.000s 811.479us 1 1 100.00
lc_ctrl_jtag_prog_failure 6.000s 1723.219us 1 1 100.00
lc_ctrl_jtag_errors 17.000s 2425.651us 1 1 100.00
lc_ctrl_jtag_access 7.000s 544.499us 1 1 100.00
lc_ctrl_jtag_regwen_during_op 22.000s 5656.217us 1 1 100.00
lc_ctrl_jtag_csr_hw_reset 2.000s 116.094us 1 1 100.00
lc_ctrl_jtag_csr_rw 2.000s 71.854us 1 1 100.00
lc_ctrl_jtag_csr_bit_bash 7.000s 3740.931us 1 1 100.00
lc_ctrl_jtag_csr_aliasing 3.000s 884.223us 1 1 100.00
lc_ctrl_jtag_same_csr_outstanding 2.000s 392.778us 1 1 100.00
lc_ctrl_jtag_csr_mem_rw_with_rand_reset 2.000s 852.967us 1 1 100.00
lc_ctrl_jtag_alert_test 2.000s 158.111us 1 1 100.00
jtag_priority 1 1 100.00
lc_ctrl_jtag_priority 5.000s 308.557us 1 1 100.00
lc_ctrl_volatile_unlock 1 1 100.00
lc_ctrl_volatile_unlock_smoke 2.000s 44.941us 1 1 100.00
stress_all 1 1 100.00
lc_ctrl_stress_all 40.000s 4104.182us 1 1 100.00
alert_test 1 1 100.00
lc_ctrl_alert_test 2.000s 19.600us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
lc_ctrl_tl_errors 3.000s 80.543us 1 1 100.00
tl_d_illegal_access 1 1 100.00
lc_ctrl_tl_errors 3.000s 80.543us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
lc_ctrl_csr_hw_reset 1.000s 69.279us 1 1 100.00
lc_ctrl_csr_rw 2.000s 46.591us 1 1 100.00
lc_ctrl_csr_aliasing 2.000s 21.827us 1 1 100.00
lc_ctrl_same_csr_outstanding 3.000s 149.676us 1 1 100.00
tl_d_partial_access 4 4 100.00
lc_ctrl_csr_hw_reset 1.000s 69.279us 1 1 100.00
lc_ctrl_csr_rw 2.000s 46.591us 1 1 100.00
lc_ctrl_csr_aliasing 2.000s 21.827us 1 1 100.00
lc_ctrl_same_csr_outstanding 3.000s 149.676us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
lc_ctrl_sec_cm 3.000s 125.098us 1 1 100.00
lc_ctrl_tl_intg_err 3.000s 741.362us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
lc_ctrl_tl_intg_err 3.000s 741.362us 1 1 100.00
sec_cm_transition_config_regwen 1 1 100.00
lc_ctrl_regwen_during_op 4.000s 820.510us 1 1 100.00
sec_cm_manuf_state_sparse 2 2 100.00
lc_ctrl_state_failure 8.000s 1356.326us 1 1 100.00
lc_ctrl_sec_cm 3.000s 125.098us 1 1 100.00
sec_cm_transition_ctr_sparse 2 2 100.00
lc_ctrl_state_failure 8.000s 1356.326us 1 1 100.00
lc_ctrl_sec_cm 3.000s 125.098us 1 1 100.00
sec_cm_manuf_state_bkgn_chk 2 2 100.00
lc_ctrl_state_failure 8.000s 1356.326us 1 1 100.00
lc_ctrl_sec_cm 3.000s 125.098us 1 1 100.00
sec_cm_transition_ctr_bkgn_chk 2 2 100.00
lc_ctrl_state_failure 8.000s 1356.326us 1 1 100.00
lc_ctrl_sec_cm 3.000s 125.098us 1 1 100.00
sec_cm_state_config_sparse 2 2 100.00
lc_ctrl_state_failure 8.000s 1356.326us 1 1 100.00
lc_ctrl_sec_cm 3.000s 125.098us 1 1 100.00
sec_cm_main_fsm_sparse 2 2 100.00
lc_ctrl_state_failure 8.000s 1356.326us 1 1 100.00
lc_ctrl_sec_cm 3.000s 125.098us 1 1 100.00
sec_cm_kmac_fsm_sparse 2 2 100.00
lc_ctrl_state_failure 8.000s 1356.326us 1 1 100.00
lc_ctrl_sec_cm 3.000s 125.098us 1 1 100.00
sec_cm_main_fsm_local_esc 2 2 100.00
lc_ctrl_state_failure 8.000s 1356.326us 1 1 100.00
lc_ctrl_sec_cm 3.000s 125.098us 1 1 100.00
sec_cm_main_fsm_global_esc 1 1 100.00
lc_ctrl_security_escalation 5.000s 633.804us 1 1 100.00
sec_cm_main_ctrl_flow_consistency 2 2 100.00
lc_ctrl_state_post_trans 4.000s 407.452us 1 1 100.00
lc_ctrl_jtag_state_post_trans 10.000s 811.479us 1 1 100.00
sec_cm_intersig_mubi 1 1 100.00
lc_ctrl_sec_mubi 13.000s 871.393us 1 1 100.00
sec_cm_token_valid_ctrl_mubi 1 1 100.00
lc_ctrl_sec_mubi 13.000s 871.393us 1 1 100.00
sec_cm_token_digest 1 1 100.00
lc_ctrl_sec_token_digest 7.000s 2017.747us 1 1 100.00
sec_cm_token_mux_ctrl_redun 1 1 100.00
lc_ctrl_sec_token_mux 4.000s 845.224us 1 1 100.00
sec_cm_token_valid_mux_redun 1 1 100.00
lc_ctrl_sec_token_mux 4.000s 845.224us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 0 1 0.00
lc_ctrl_stress_all_with_rand_reset 31.000s 4107.568us 0 1 0.00

Error Messages

   Test seed line log context
UVM_ERROR (cip_base_vseq.sv:1237) [lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses.
lc_ctrl_stress_all_with_rand_reset 41444008910147192531062348374081783107706303211366067416092973198249191530669 185
UVM_ERROR @ 4107568070 ps: (cip_base_vseq.sv:1237) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 4107568070 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---