Simulation Results: mbx

 
07/04/2026 16:08:41 DVSim: v1.17.3 sha: ae672c6 json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 90.56 %
  • code
  • 89.90 %
  • assert
  • 96.57 %
  • func
  • 85.21 %
  • block
  • 96.06 %
  • line
  • 95.68 %
  • branch
  • 89.55 %
  • toggle
  • 84.46 %
Validation stages
V1
100.00%
V2
81.82%
V2S
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
mbx_smoke 1 1 100.00
mbx_smoke 20.000s 1074.885us 1 1 100.00
csr_hw_reset 1 1 100.00
mbx_csr_hw_reset 1.000s 38.486us 1 1 100.00
csr_rw 1 1 100.00
mbx_csr_rw 2.000s 14.319us 1 1 100.00
csr_bit_bash 1 1 100.00
mbx_csr_bit_bash 3.000s 218.340us 1 1 100.00
csr_aliasing 1 1 100.00
mbx_csr_aliasing 2.000s 13.550us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
mbx_csr_mem_rw_with_rand_reset 2.000s 83.080us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
mbx_csr_rw 2.000s 14.319us 1 1 100.00
mbx_csr_aliasing 2.000s 13.550us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
mbx_stress 1 1 100.00
mbx_stress 133.000s 26715.071us 1 1 100.00
mbx_max_activity 0 1 0.00
mbx_stress_zero_delays 4.000s 685.305us 0 1 0.00
mbx_imbx_oob 1 1 100.00
mbx_imbx_oob 48.000s 22089.691us 1 1 100.00
mbx_doe_intr_msg 1 1 100.00
mbx_doe_intr_msg 9.000s 653.792us 1 1 100.00
alert_test 1 1 100.00
mbx_alert_test 2.000s 46.896us 1 1 100.00
intr_test 1 1 100.00
mbx_intr_test 2.000s 26.932us 1 1 100.00
tl_d_oob_addr_access 0 1 0.00
mbx_tl_errors 1.000s 18.892us 0 1 0.00
tl_d_illegal_access 0 1 0.00
mbx_tl_errors 1.000s 18.892us 0 1 0.00
tl_d_outstanding_access 4 4 100.00
mbx_csr_hw_reset 1.000s 38.486us 1 1 100.00
mbx_csr_rw 2.000s 14.319us 1 1 100.00
mbx_csr_aliasing 2.000s 13.550us 1 1 100.00
mbx_same_csr_outstanding 2.000s 19.867us 1 1 100.00
tl_d_partial_access 4 4 100.00
mbx_csr_hw_reset 1.000s 38.486us 1 1 100.00
mbx_csr_rw 2.000s 14.319us 1 1 100.00
mbx_csr_aliasing 2.000s 13.550us 1 1 100.00
mbx_same_csr_outstanding 2.000s 19.867us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
mbx_sec_cm 1.000s 38.375us 1 1 100.00
mbx_tl_intg_err 2.000s 277.505us 1 1 100.00

Error Messages

   Test seed line log context
xmsim: *E,ASRTST (/nightly/current_run/scratch/master/mbx-sim-xcelium/default/fusesoc-work/src/lowrisc_ip_mbx_*/rtl/mbx_ombx.sv,287): Assertion ReadyAssertedWhenRead_A has failed
mbx_stress_zero_delays 83597767659924015327131186416577367917638238399678374607990251526917974765859 243
xmsim: *E,ASRTST (/nightly/current_run/scratch/master/mbx-sim-xcelium/default/fusesoc-work/src/lowrisc_ip_mbx_0.1/rtl/mbx_ombx.sv,287): (time 685305148 PS) Assertion tb.dut.u_ombx.ReadyAssertedWhenRead_A has failed
UVM_ERROR @ 685305148 ps: (mbx_ombx.sv:287) [ASSERT FAILED] ReadyAssertedWhenRead_A
UVM_INFO @ 685305148 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_scoreboard.sv:582) scoreboard [scoreboard] On interface mbx_soc_reg_block, item had unexpected d_error value(predicted *, but saw *).
mbx_tl_errors 26506649746554493768402194735611970080129452311015499454689695195881559626171 85
UVM_ERROR @ 18891506 ps: (cip_base_scoreboard.sv:582) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] On interface mbx_soc_reg_block, item had unexpected d_error value(predicted 1, but saw 0).
TL item was: req: (cip_tl_seq_item@15750) { a_addr: 'hf3c35dd4 a_data: 'h9152c57b a_mask: 'h7 a_size: 'h2 a_param: 'h0 a_source: 'hd a_opcode: 'h1 a_user: 'h2461c d_param: 'h0 d_source: 'hd d_data: 'h0 d_size: 'h2 d_opcode: 'h0 d_error: 'h0 d_sink: 'h0 d_user: 'h1caa a_valid_delay: 'h0 d_valid_delay: 'h0 a_valid_len: 'h0 d_valid_len: 'h0 req_abort_after_a_valid_len: 'h0 rsp_abort_after_d_valid_len: 'h0 req_completed: 'h0 rsp_completed: 'h0 tl_intg_err_type: TlIntgErrNone max_ecc_errors: 'h3 }
Reasons for predicted error: '{"Unsupported partial write"}.
UVM_INFO @ 18891506 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---