Simulation Results: rom_ctrl/64kb

 
07/04/2026 16:08:41 DVSim: v1.17.3 sha: ae672c6 json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 95.63 %
  • code
  • 94.33 %
  • assert
  • 96.79 %
  • func
  • 95.76 %
  • block
  • 95.91 %
  • line
  • 96.33 %
  • branch
  • 93.82 %
  • toggle
  • 87.16 %
  • FSM
  • 100.00 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
rom_ctrl_smoke 8.000s 566.590us 1 1 100.00
csr_hw_reset 1 1 100.00
rom_ctrl_csr_hw_reset 7.000s 470.067us 1 1 100.00
csr_rw 1 1 100.00
rom_ctrl_csr_rw 5.000s 213.953us 1 1 100.00
csr_bit_bash 1 1 100.00
rom_ctrl_csr_bit_bash 5.000s 207.838us 1 1 100.00
csr_aliasing 1 1 100.00
rom_ctrl_csr_aliasing 4.000s 214.979us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
rom_ctrl_csr_mem_rw_with_rand_reset 5.000s 566.400us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
rom_ctrl_csr_rw 5.000s 213.953us 1 1 100.00
rom_ctrl_csr_aliasing 4.000s 214.979us 1 1 100.00
mem_walk 1 1 100.00
rom_ctrl_mem_walk 6.000s 1272.088us 1 1 100.00
mem_partial_access 1 1 100.00
rom_ctrl_mem_partial_access 6.000s 212.832us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
max_throughput_chk 1 1 100.00
rom_ctrl_max_throughput_chk 5.000s 876.456us 1 1 100.00
stress_all 1 1 100.00
rom_ctrl_stress_all 16.000s 771.768us 1 1 100.00
kmac_err_chk 1 1 100.00
rom_ctrl_kmac_err_chk 8.000s 1231.074us 1 1 100.00
alert_test 1 1 100.00
rom_ctrl_alert_test 5.000s 3555.511us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
rom_ctrl_tl_errors 6.000s 1027.012us 1 1 100.00
tl_d_illegal_access 1 1 100.00
rom_ctrl_tl_errors 6.000s 1027.012us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
rom_ctrl_csr_hw_reset 7.000s 470.067us 1 1 100.00
rom_ctrl_csr_rw 5.000s 213.953us 1 1 100.00
rom_ctrl_csr_aliasing 4.000s 214.979us 1 1 100.00
rom_ctrl_same_csr_outstanding 7.000s 545.512us 1 1 100.00
tl_d_partial_access 4 4 100.00
rom_ctrl_csr_hw_reset 7.000s 470.067us 1 1 100.00
rom_ctrl_csr_rw 5.000s 213.953us 1 1 100.00
rom_ctrl_csr_aliasing 4.000s 214.979us 1 1 100.00
rom_ctrl_same_csr_outstanding 7.000s 545.512us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
corrupt_sig_fatal_chk 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 69.000s 3754.124us 1 1 100.00
passthru_mem_tl_intg_err 1 1 100.00
rom_ctrl_passthru_mem_tl_intg_err 14.000s 4624.457us 1 1 100.00
tl_intg_err 2 2 100.00
rom_ctrl_tl_intg_err 24.000s 751.621us 1 1 100.00
rom_ctrl_sec_cm 182.000s 6276.802us 1 1 100.00
prim_fsm_check 1 1 100.00
rom_ctrl_sec_cm 182.000s 6276.802us 1 1 100.00
prim_count_check 1 1 100.00
rom_ctrl_sec_cm 182.000s 6276.802us 1 1 100.00
sec_cm_checker_ctr_consistency 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 69.000s 3754.124us 1 1 100.00
sec_cm_checker_ctrl_flow_consistency 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 69.000s 3754.124us 1 1 100.00
sec_cm_checker_fsm_local_esc 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 69.000s 3754.124us 1 1 100.00
sec_cm_compare_ctrl_flow_consistency 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 69.000s 3754.124us 1 1 100.00
sec_cm_compare_ctr_consistency 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 69.000s 3754.124us 1 1 100.00
sec_cm_compare_ctr_redun 1 1 100.00
rom_ctrl_sec_cm 182.000s 6276.802us 1 1 100.00
sec_cm_fsm_sparse 1 1 100.00
rom_ctrl_sec_cm 182.000s 6276.802us 1 1 100.00
sec_cm_mem_scramble 1 1 100.00
rom_ctrl_smoke 8.000s 566.590us 1 1 100.00
sec_cm_mem_digest 1 1 100.00
rom_ctrl_smoke 8.000s 566.590us 1 1 100.00
sec_cm_intersig_mubi 1 1 100.00
rom_ctrl_smoke 8.000s 566.590us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
rom_ctrl_tl_intg_err 24.000s 751.621us 1 1 100.00
sec_cm_bus_local_esc 2 2 100.00
rom_ctrl_corrupt_sig_fatal_chk 69.000s 3754.124us 1 1 100.00
rom_ctrl_kmac_err_chk 8.000s 1231.074us 1 1 100.00
sec_cm_mux_mubi 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 69.000s 3754.124us 1 1 100.00
sec_cm_mux_consistency 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 69.000s 3754.124us 1 1 100.00
sec_cm_ctrl_redun 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 69.000s 3754.124us 1 1 100.00
sec_cm_ctrl_mem_integrity 1 1 100.00
rom_ctrl_passthru_mem_tl_intg_err 14.000s 4624.457us 1 1 100.00
sec_cm_tlul_fifo_ctr_redun 1 1 100.00
rom_ctrl_sec_cm 182.000s 6276.802us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 1 1 100.00
rom_ctrl_stress_all_with_rand_reset 51.000s 2464.942us 1 1 100.00