Simulation Results: rstmgr

 
07/04/2026 16:08:41 DVSim: v1.17.3 sha: ae672c6 json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 90.71 %
  • code
  • 78.50 %
  • assert
  • 95.68 %
  • func
  • 97.96 %
  • block
  • 90.11 %
  • line
  • 89.53 %
  • branch
  • 82.20 %
  • toggle
  • 97.27 %
  • FSM
  • 45.02 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
rstmgr_smoke 3.000s 59.351us 1 1 100.00
csr_hw_reset 1 1 100.00
rstmgr_csr_hw_reset 2.000s 64.229us 1 1 100.00
csr_rw 1 1 100.00
rstmgr_csr_rw 1.000s 37.831us 1 1 100.00
csr_bit_bash 1 1 100.00
rstmgr_csr_bit_bash 4.000s 196.345us 1 1 100.00
csr_aliasing 1 1 100.00
rstmgr_csr_aliasing 2.000s 43.673us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
rstmgr_csr_mem_rw_with_rand_reset 1.000s 65.045us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
rstmgr_csr_rw 1.000s 37.831us 1 1 100.00
rstmgr_csr_aliasing 2.000s 43.673us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
reset_stretcher 1 1 100.00
rstmgr_por_stretcher 1.000s 76.677us 1 1 100.00
sw_rst 1 1 100.00
rstmgr_sw_rst 2.000s 37.731us 1 1 100.00
sw_rst_reset_race 1 1 100.00
rstmgr_sw_rst_reset_race 2.000s 65.349us 1 1 100.00
reset_info 1 1 100.00
rstmgr_reset 7.000s 572.592us 1 1 100.00
cpu_info 1 1 100.00
rstmgr_reset 7.000s 572.592us 1 1 100.00
alert_info 1 1 100.00
rstmgr_reset 7.000s 572.592us 1 1 100.00
reset_info_capture 1 1 100.00
rstmgr_reset 7.000s 572.592us 1 1 100.00
stress_all 1 1 100.00
rstmgr_stress_all 50.000s 6932.039us 1 1 100.00
alert_test 1 1 100.00
rstmgr_alert_test 2.000s 36.897us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
rstmgr_tl_errors 3.000s 74.436us 1 1 100.00
tl_d_illegal_access 1 1 100.00
rstmgr_tl_errors 3.000s 74.436us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
rstmgr_csr_hw_reset 2.000s 64.229us 1 1 100.00
rstmgr_csr_rw 1.000s 37.831us 1 1 100.00
rstmgr_csr_aliasing 2.000s 43.673us 1 1 100.00
rstmgr_same_csr_outstanding 1.000s 71.836us 1 1 100.00
tl_d_partial_access 4 4 100.00
rstmgr_csr_hw_reset 2.000s 64.229us 1 1 100.00
rstmgr_csr_rw 1.000s 37.831us 1 1 100.00
rstmgr_csr_aliasing 2.000s 43.673us 1 1 100.00
rstmgr_same_csr_outstanding 1.000s 71.836us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
rstmgr_sec_cm 18.000s 3424.665us 1 1 100.00
rstmgr_tl_intg_err 2.000s 417.050us 1 1 100.00
prim_count_check 1 1 100.00
rstmgr_sec_cm 18.000s 3424.665us 1 1 100.00
prim_fsm_check 1 1 100.00
rstmgr_sec_cm 18.000s 3424.665us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
rstmgr_tl_intg_err 2.000s 417.050us 1 1 100.00
sec_cm_scan_intersig_mubi 1 1 100.00
rstmgr_sec_cm_scan_intersig_mubi 2.000s 60.269us 1 1 100.00
sec_cm_leaf_rst_bkgn_chk 1 1 100.00
rstmgr_leaf_rst_cnsty 4.000s 421.180us 1 1 100.00
sec_cm_leaf_rst_shadow 1 1 100.00
rstmgr_leaf_rst_shadow_attack 3.000s 292.036us 1 1 100.00
sec_cm_leaf_fsm_sparse 1 1 100.00
rstmgr_sec_cm 18.000s 3424.665us 1 1 100.00
sec_cm_sw_rst_config_regwen 1 1 100.00
rstmgr_csr_rw 1.000s 37.831us 1 1 100.00
sec_cm_dump_ctrl_config_regwen 1 1 100.00
rstmgr_csr_rw 1.000s 37.831us 1 1 100.00